We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Participant sarit8
Registered: ‎08-15-2016

How can I integrate the The PCI Express® Root Port Model in my tes tbecnh?

I use vivado 2016.2. I executed export simulation for xilinx_axi_pcie_ep.


I have a test bech which contain my dut which has an axi-bridge-pcie.The axi-bridge-pcie is connected AXI Inter Connect (with axi4 protocl), and to DMA.


In my current test bench I connect with force to the axi protocol (btween the axi-bridge-pcie AXI Inter Connect, and send read and write transacrion.

How can I add option that instead of above I will send the read and write transacrion fron the axi-bridge-pcie by connecting it to the  PCI Express® Root Port Model.


Visioo of my tb is attached:

0 Kudos