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Participant sarit8
Participant
629 Views
Registered: ‎08-15-2016

How can I integrate the The PCI Express® Root Port Model in my tes tbecnh?

I use vivado 2016.2. I executed export simulation for xilinx_axi_pcie_ep.

 

I have a test bech which contain my dut which has an axi-bridge-pcie.The axi-bridge-pcie is connected AXI Inter Connect (with axi4 protocl), and to DMA.

 

In my current test bench I connect with force to the axi protocol (btween the axi-bridge-pcie AXI Inter Connect, and send read and write transacrion.

How can I add option that instead of above I will send the read and write transacrion fron the axi-bridge-pcie by connecting it to the  PCI Express® Root Port Model.

 

Visioo of my tb is attached:

axi_t.PNG
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