09-22-2019 05:36 AM
I am trying to run a simple systemC simulation in Vivado.
First of all the Doccumention in UG900 Appendix D seems to have a couple of issues.
1) The xsc command adds "xsim.dir" to the path for the compile output directory. This isn't mentioned in the docs. (This would seem to make the two stage instructions incorrect).
2) It appears that the the command line argument to point to the C compiled stuff should be -sc_lib.
Anyhow the main issue I am having is getting xelab to work.
If I compile with default seetings other adding -gcc_comile_options to find included files I get a succesful compilation.
However xelab errors out complaining that there is no top level specified. I have tried several options with the command line switches and always get the same error.
09-22-2019 11:58 PM
Are you trying to run systemC simulation in Vivado? Can you please confirm. I hope you are referring to the DPI flow where you can use the SystemVerilog Direct Programming Interface (DPI) to bind C code to SystemVerilog code. Using DPI, SystemVerilog code can call a C function, which in turn can call back a SystemVerilog task or function as described in Appendix D of UG900.
If you are using DPI flow then can you please check with the examples of DPI in install directory <Vivado installation directory>/examples/xsim/systemverilog/dpi and see if it helps.
Also, please note that the -svlib option is used for the Name of the DPI shared library without the file extension (.dll/.so) and the -sc_lib option is used for the Shared library name for SystemC functions.
Can you please share the script files with commands used and with the steps you have followed to check this issue at my end.
09-23-2019 07:23 AM
Yes I am trying to run a systemC simulation in Vivado.
I am attemting to run a pure systemC testbench which could then connect to an RTL DUT (IN either systemC VHDL or Verilog).
I was simpy using xsc to compile the code.
xsc --gcc_compile_option -I ../src ../tb/tb.cpp
xelab -sc_lib dpi
Does this require a System Verilog top level?
09-25-2019 11:04 AM
I have done some more digging through the exaples and gone over UG900 appendix D and I.
I think I have a bit of an understanding of it now. These are my conclusions.
1) You need to use DPI any time C code (I assume this incluses systemC) is referenced by a system Verilog file
VHDL top seems to not be supported.
2) You need to use XSI any time VHDL or Verilog is instantiated under a C (And I assume SystemC) test bench.
3) In both cases the simulation runs standalone and thus looses any debugging facilities that running it in the Vivado Simulator provides
4) The only waveform tracing supported would be through SC_TRACE in the systemC modules.
Given this the idea of building a systemC testbench for use interchangably with SystemC or Verilog or VHDL DUTs seems not very workable.
Any feedback on this would be gratly appreciated.