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vishysub
Participant
Participant
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Registered: ‎11-03-2010

How to feed a clock signal to simulate a module

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I have a verilog module as under

 

module test(
    input    rst,
    input    clk,
    input    en,
    input [7:0] data,
    output    s1,
    output    s2
    );

 

I want to test it in Isim, for this I would like to feed a clock signal of say 100Khz to it, does Isim have any inbuilt sources to connect, or do I have to write my own sample test code to generate that clock and feed it to the module?

 

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edv
Xilinx Employee
Xilinx Employee
56,259 Views
Registered: ‎08-15-2007

If using ISim 12.1 and newer, you can use "Force Clock" to actually generate a clock during simulation, without writing a testbench.  This is useful when you need to do just that: create a clock.  There's also a "Force Constant" to then drive discrete values to signals/buses.  

 

For more information, check out the ISim User Guide.  

 

Also, check out the video tutorial on this at http://www.youtube.com/watch?v=j3er7wVM984, at about 3min 30secs.

 

Hope this helps.

Eddie

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gszakacs
Professor
Professor
41,211 Views
Registered: ‎08-14-2007

You need to write a testbench to stimulate the design.  If you're not familiar with

writing a test bench, the easiest way to get started is to use the ISE Navigator

 

Project --> New Source

select "Verilog Test Fixture"

Give it an amusing name like test_tb

Associate it with the module to test (test.v)

 

You will get a file that contains declarations of "reg" type for all your

input ports, and "wire" type for all of the other ports of your unit under

test.  It also has an instantiation of your code named "uut" and an

"initial" block to initialize all of the inputs to zero.

 

Then hack on this module as follows:

Change the initial value of your inputs as appropriate in the

initial block.  For example anything that doesn't need to change

under normal testing conditions can have its default value,

but you probably want to assert the reset imput at time zero

and then de-assert it after at least 100 ns (this is important!

all instantiated primitives get held in their INIT state for the

first 100 ns of simulation).

 

For a clock, you can just add a line to toggle it (outside the

initial block) like:

 

always clk = #5 ~clk;  // 100 MHz

 

HTH,

Gabor

-- Gabor
edv
Xilinx Employee
Xilinx Employee
56,260 Views
Registered: ‎08-15-2007

If using ISim 12.1 and newer, you can use "Force Clock" to actually generate a clock during simulation, without writing a testbench.  This is useful when you need to do just that: create a clock.  There's also a "Force Constant" to then drive discrete values to signals/buses.  

 

For more information, check out the ISim User Guide.  

 

Also, check out the video tutorial on this at http://www.youtube.com/watch?v=j3er7wVM984, at about 3min 30secs.

 

Hope this helps.

Eddie

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vishysub
Participant
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Registered: ‎11-03-2010

Hello,

Many thanks, I went through the video and followed the steps given.

 

I have sent the clk with force clock to 100khz

However I find that

 

  1. The variables do not change when I step over them.

 

For instance I have declared something like

 

Counter_n [0:3]  = xxxx

 

 

 

And after stepping over 

 counter_t <= counter_t + 1;

 

 

 

It still stays xxxx.

 

Not sure what I'm doing wrong. Will the value be latched on the next clock cycle?

 

  1. The timescale in the source is 1ns/1ps and the simulator shows time in very small res(something like in 1ps steps
    I want to change this to 10us steps so do I need to change the timescale for this or is there an alternate setting in Isim to change the time resolution?

 

Rgds

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awillen
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41,168 Views
Registered: ‎11-29-2007
 counter_t <= counter_t + 1;

This is a concurrent assignment. It's effect is scheduled to be visible after all other concurrent assignments of the current step have been executed.

 

 

The zoom in the wave form window is not affected by the timescale. Instead, use F7 and F8 to zoom in and out.

 

 

Adrian



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vishysub
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Registered: ‎11-03-2010

 


This is a concurrent assignment. It's effect is scheduled to be visible after all other concurrent assignments of the current step have been executed.

 

Adrian


 

I'm not sure what this means.

By "current step" do you mean all the non blocking statements in the current module, or all non blocking statements in all modules?

 

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awillen
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Registered: ‎11-29-2007

All the non-blocking assignments which are executed at the current simulation time, from all modules.



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vishysub
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Registered: ‎11-03-2010

I simulated for upto 6 clock cycles and the variable "counter_t" still shows "xxxx". What could I be doing wrong, other variables are getting updated in the variable window except this variable, and this variable is changed on this line amongst others.

 

 

		 counter_t <= counter_t + 1;

 

any idea what could be going wrong?

 

 

 

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gszakacs
Professor
Professor
41,144 Views
Registered: ‎08-14-2007

Actually the problem has nothing to do with non-blocking assignments.  What

value do you expect when you add 0001 to xxxx?  If you don't know the value

before adding one, you still don't know the value afterwards.  If you want to

simulate a counter, you will need to initialize it.  You can do this in the dclaration

like:

 

reg [3:0] count = 4'b0;

 

or you can use a reset term like

 

always @ (posedge clk)

  if (rst) count <= 4'b0;

  else if (ce) count <= count + 1;

 

Then assuming your testbench asserts rst for at least one clock cycle,

your counter will start at zero and count up.

 

HTH,

Gabor

-- Gabor
awillen
Mentor
Mentor
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Registered: ‎11-29-2007

I'm sorry, I totally overlooked the "xxxx" part. "X" means undefined, and if you add 1 to an undefined value, you get undefined – what else did you expect? Initialize your counter with 0.

 

 

Adrian



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vishysub
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Many thanks! don't believe I missed that too, while concentrating on Verilog I forgot the basics.

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vishysub
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Hello Gabor,

I am currently trying your technique of the test bench.

So in the Project -> New Source > Verilog Test Fixture I generate a new test bench file and this new file appears only in the simulation tab and not in the implementation.

 

After doing this I recompiled, synthesized my code and then ran Isim however it doesn't run as intended. I mean I don't get any breakpoints that  I have set in my code.

 

As you suggested I added 

always clk = #50 ~clk;  // 100 kHz

 Funnily in Isim only the test.v and some other file name glbl.v show up in the source options, it seems the testbench file doesn't get included in the project or something on those lines?

 

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awillen
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So in the Project -> New Source > Verilog Test Fixture I generate a new test bench file and this new file appears only in the simulation tab and not in the implementation.

 

Well, duh! It is only useful for simulation, so why should it appear in the implementation tab?

 

 


After doing this I recompiled, synthesized my code and then ran Isim however it doesn't run as intended. I mean I don't get any breakpoints that  I have set in my code.

 

Are there blue lines in the wave form window? If yes, then you've selected the wrong file. Select the testbench module before you double-click on "Simulate".

 

 


always clk = #50 ~clk; // 100 kHz

Assuming you kept the standard timescale directive, then that's a 10 MHz clock, not a 100 kHz one.

 

 

Adrian



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vishysub
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Registered: ‎11-03-2010

You were right, I probably selected the wrong file!

 

Many thanks!!

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