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Visitor
Visitor
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Registered: ‎12-04-2018

How to generate MMCM simulation library for logic simulation in ModelSim DE

I use ModelSim DE (64 bit windows) for logic simulation.
I use MMCM (clk_wiz_0) created from IP catalog for my design.
However, I do not know how to generate the MMCM logic simulation library.
Please tell me how to generate MMCM simulation library for logic simulation in ModelSim DE.

I will attach an MMCM specification for my design. I want to generate a logic simulation library for this MMCM ModelSim DE.

Best Regrads,

mmcm usig my design.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: How to generate MMCM simulation library for logic simulation in ModelSim DE

You need to run Tcl command 'compile_simlib' to compile Vivado simulaiton libraries for 3rd party tools.

This can be launched from Vivado GUI Tools > Compile Simulation Libraries..., or manually run the command from Tcl console. 

For its usage, type 'compile_simlib -help' for help manual.

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Visitor
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Registered: ‎12-04-2018

回复: How to generate MMCM simulation library for logic simulation in ModelSim DE

Thank you for your reply.I ran the Compile Simulation Libraries. But I can not find the folder of MMCM. Which folder should I choose for the MMCM simulation library?I attached a folder list. Please tell me the folder I should select.

Best Regrards,

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: How to generate MMCM simulation library for logic simulation in ModelSim DE

The MMCM cell is within library unisim (VHDL) or unisims_ver (Verilog).

If you run simulation in Modelsim standalone, you need to load the library via -L switch.

If you launch simulation from within Vivado GUI, the tool will generate appropriate simulation script and start Modelsim GUI.

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Visitor
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Registered: ‎12-04-2018

回复: How to generate MMCM simulation library for logic simulation in ModelSim DE

I use ModelSim standalone. And I run logic simulation using command mode in ModelSim.
I use verilog.I loaded the unisims_ver using the L switch. But there is no permission. I do not know the solution. Please tell me how to resolve the error.
 
I will attach unisims_v folder list and an error screen.
 
Best Regrards
library folder list.jpg
err screen.jpg
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Xilinx Employee
Xilinx Employee
376 Views
Registered: ‎07-16-2008

回复: How to generate MMCM simulation library for logic simulation in ModelSim DE

The -L (capital letter) switch is expected to be used in vopt/vsim, e.g. -L unisims_ver

You need to put the modelsim.ini that compile_simlib generates into the current simulation directory. This allows Modelsim to search the pre-compiled libraries. 

I'd suggest that you run export_simulation command (or File > Export > Export Simulation) in Vivado to export a simulation script for the Vivado project targetting Modelsim. Use that as a starting point for your own one.

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