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Contributor
Contributor
247 Views
Registered: ‎06-07-2012

How to get mapped address from block design into SystemVerilog simulation

Hi,

 

I am trying to automate the simulation process and the addresses of the various components are hardcoded in the simulation code.  I would like to get the address of the component from the block design into the SystemVerilog in an automated way instead of having it hardcoded at 2 places (in the IP integrator window and in the testbench).

 

The close I can get is to use a .tcl script on the block design which get the offset property, like:

get_property offset [get_bd_addr_segs {processing_system7_0/Data/SEG_AxiSlave2RegFile_0_S00_AXI_reg}] 

 

The TCL script could then write the offset into a verilog header file that can be included in the verilog simulation.

 

Anybody has a simpler way?

 

Thanks,

 

jf

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1 Reply
Moderator
Moderator
190 Views
Registered: ‎04-24-2013

Re: How to get mapped address from block design into SystemVerilog simulation

Hi @jlarin,

There is no simpler way to get the offset that I know if, but you could try using the -generic_top <value> option in the xelab e.g. -generic_top "P1=10"

As per UG900

Generics (Parameters) Mapping
The Vivado simulator supports the following VHDL generic types (and their Verilog/SV
equivalents):
• integer
• real
• string
• boolean
Note: Any other generic type found on mixed language boundary is considered an error.

Best Regards
Aidan

 

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