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Observer
Observer
799 Views
Registered: ‎03-14-2017

How to initialize RAM ports SYNC/ASYNC etc

 

I am trying to connect the RAM ports in my design and the choices are known. 

How to get the corresponding parameter value for the choices? 

 

RAMB16BWER #(
// DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
.DATA_WIDTH_A(9),
.DATA_WIDTH_B(9),
// DOA_REG/DOB_REG: Optional output register (0 or 1)
.DOA_REG(0),
.DOB_REG(0),
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
.EN_RSTRAM_A(true),
.EN_RSTRAM_B(true),
// INIT_A/INIT_B: Initial values on output port
.INIT_A(36'h 000000000),
.INIT_B(36'h 000000000),
// INIT_FILE: Optional file used to specify initial RAM contents
//.INIT_FILE(), -- Ram how to load this file
// RSTTYPE: "SYNC" or "ASYNC"
//.RSTTYPE(4'b SYNC), -- ?
.RSTTYPE(4'b0),
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
//.RST_PRIORITY_A(2'b CE), --?
.RST_PRIORITY_A(2'b00),
.RST_PRIORITY_B(2'b CE), --?
// SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
.SIM_COLLISION_CHECK(3'b ALL), --?
// SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
.SIM_DEVICE(8'b SPARTAN6), --?
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
.SRVAL_A(36'h 000000000),
.SRVAL_B(36'h 000000000),
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
.WRITE_MODE_A(11'b WRITE_FIRST), --?
.WRITE_MODE_B(11'b WRITE_FIRST)) --?

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Scholar
Scholar
776 Views
Registered: ‎03-22-2016

@ramp69 see page 246 here

http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_4/spartan6_hdl.pdf

 

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Moderator
Moderator
747 Views
Registered: ‎11-09-2015

Hi @ramp69,

 

The simplest for you might be to use a block memory generator IP which will instantiate the RAM for you. You might want to read PG058.

 

Else, if you really want to understand the parameter of the macro for the RAM, you can check the UG on memory ressources for your device (ex UG473 on 7-series)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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