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Visitor
Visitor
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Registered: ‎08-24-2018

How to initialize the ROM memory in Post PAR verilog netlist without implementation again

I just want to run the post PAR simulation, but I got several ROM test codes. Does anybody know how to generated the new post PAR verilog netlist with the different rom codes. I don't want to do the implementation operation again and again. it takes too long time.

 

Actually,  I could use data2mem to generate one new verilog defparam file liking: 

defparam u_chip.wakeupmix.rom_128k.rom_128k.u_rom.U0.xst_blk_mem_generator.gnativebmg.native_blk_mem_gen.valid.cstr.ramloop[0].ram.r.v6_init.ram.NO_BMM_INFO.SP.INIT_00  = 256'h00200E9500200E9500200E9500200E9500200E9500200E95002004112001FFF8;

 

it seems that was some kind of initialization codes for my simulation model. but when I copy those codes to my testbench file, it seem that it does not work. how to use this file generated by data2mem program?

 

BTW, the data2mem is old program supported by ISE. what's the tool name support similar function in current vivado version?

 

Thanks a lot. 

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Moderator
Moderator
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Registered: ‎05-31-2017

Hi @hansen_bai,

 

Can you once check the below AR and see if it helps

https://www.xilinx.com/support/answers/63041.html

 

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