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mighty
Visitor
Visitor
1,573 Views
Registered: ‎12-05-2017

How to instantiate the ddr4_model.sv in my testbench?

I've generated a vivado DDR4 SDRAM IP core and want to simulate the DDR4 memory controller with my own verilog testbench. I can instantiate the DDR4 SDRAM IP core, since there is a ddr4_0.veo file which I can use, but I can't instantiate the ddr4_model because it's encrypted and I don't know the input and output ports of it. I wonder how I can instantiate the ddr4 simulation model in my verilog testbench. Can anyone help me out? Thanks!

ddr4_model.jpg
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vemulad
Xilinx Employee
Xilinx Employee
1,559 Views
Registered: ‎09-20-2012

Hi @mighty

 

Check the IP example design test bench file for instantiation of memory model. To open example design, right click on IP and choose "open IP example design"

Thanks,
Deepika.
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