How to make sure you're using the main clock tree?

[andy92806]

This may be an obvious question, but not so obvious.  Let's say you have a module that needs a clock like this.  Then you create an upper level module that will output a clock.  How do I know the "clock" will come from the main clock tree and not from an output of a flip-flop (which is not recommended)?

module need_clk(i_clk)

{

   input i_clk;

. .......

}

module upper_level(clock)

{

   output clock;

  always
  begin
    #5 Clock = 1;
    #5 Clock = 0;
  end

}

[rshekhaw]

Hi @andy92806 ,

You can run command in tcl console:

report_clock_networks -name {network_1}

Report Clock Networks provides a tree view of the clock trees in the design. Each clock tree shows the clock network from source to endpoint with the endpoints sorted by type.

Thanks,

Raj

[andy92806]

Hi Raj,

Thank you.

Is there a way to specify or how does it is decided which clock is being used?  Can I have control over that?

Thanks.

[calibra]

Sorry but I don't understand your question.
The clock comes from where you connected it.
The compiler doesn't make it up.

[andy92806]

I know how I phrased the question may be a bit confusing but let's see if I can clarify my question.

Let's say your FPGA device has a single clock input pin.  And on the board, you supply 25MHz to that pin, so the 25MHz signal will be connected to the device clock tree.  

Let's say you have a module that needs a 25MHz clock and another module that needs a 2.5MHz clock.

I mean how does the synthesis tools determines where to route the clock to each module?  How does the synthesis tool make sure the clock comes from the main tree and not from an output of a flip-flop?

[calibra]

@andy92806

The RTL code defines perfectly and unambiguously your design.

[richardhead]

This is the simulation forum,  is this a simulation question?  The clock provided in the original post is clearly a simulation clock and cannot be generated in an fpga. The rtl tells the compiler which clock connects to which nets.

[hemangd]

@andy92806 

>>I mean how does the synthesis tools determines where to route the clock to each module?  How does the synthesis tool make sure the clock comes from the main tree and not from an output of a flip-flop?

It is not recommended to forward the clock from a flops output. 

Once you define a clock as an input port in your entity you will have to write a create_clock constraint as well for that clock name and need to specify a GC pin related to it so the tool will understand that yes this is the clock and will use dedicated routing for your clock and it will not use fabric routing for the same. 

Based on your clock constraints tool will understand that whether to take that signal as clock routing (dedicated routing) or fabric routing (flops' output or a LUT's output).

To know about basic timing constraints kindly go through this. https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html

[calibra]

Hi  @hemangd

You said "Based on your clock constraints tool will understand that whether to take that signal as clock routing (dedicated routing) or fabric routing (flops' output or a LUT's output)."

No, the RTL design define exactly the topology of the circuit independently of the timing constraints.

process
begin
wait until CLK = '1' ;
if ( RST = '1' ) then
CLK2 <= '0' ;
else
CLK2 <= not CLK2 ;
end if ;
end process ;

process
begin
wait until CLK2 = '1' ;
if ( RST = '1' ) then
Y <= '0' ;
else 
Y <= not Y ;
end if ;
end process ;

CLK is a global clock and CLK2 is always a generate clock independently of the timing constraints.

[hemangd]

@calibra 

This mentioned use case is not recommended, CLK2 is not a recommended clock because it is using fabric for its routing.

To use a global routing for a generated clock you will require to add proper basic timing constraints. 

[calibra]

@hemangd 

Of course it is only to show that the type of clock driver only depends on the RTL code and not on the timing constraints as you said on previous post.

[andy92806]

Thank you hemangd.

Let's say the 25MHz is the main clock tree.  If you also need a 2.5MHz for example, what would be the recommended way to generate a 2.5MHz clock?

Thanks.

[calibra]

@andy92806 

You want 2 clocks or a circuit with a 25Mhz clock which "run" at 2.5Mhz ?

[andy92806]

---

@calibra wrote:

@andy92806 

You want 2 clocks or a circuit with a 25Mhz clock which "run" at 2.5Mhz ?

---

Could you elaborate on that?  Unless the FPGA chip has a PLL, you would have to divide a 25MHz down to 2.5MHz?  Which means it has to come out of a flip-flop.  

[calibra]

@andy92806 The correct option is only one clock but in a previous post you ask for "If you also need a 2.5MHz for example, what would be the recommended way to generate a 2.5MHz clock?".

My question is, why do you want  a second clock ?

To decrease power ?

[andy92806]

---

@calibra wrote:

@andy92806 The correct option is only one clock but in a previous post you ask for "If you also need a 2.5MHz for example, what would be the recommended way to generate a 2.5MHz clock?".

My question is, why do you want  a second clock ?

To decrease power ?

---

Yes, I understand ideally you only want one clock but hypothetically, if you need a second clock, then it seems like it has to come out of a flip-flop.  I guess you could make sure the flip-flop output does not have a significant load that it might violate timing constraints.

[bruce_karaffa]

The proper way to handle your example is to run your logic on the 25MHz clock and make a clock enable signal that is active for one cycle out of every ten.  Use the clock enable in your code for all processes that should run at the lower rate.  The koad on a clock generated in logic is only one factor that degrades the clock.  FPGAs have dedicated, low skew clock trees.  Running a clock in logic introduces more skew and jitter and your timing will change every time you build.

[andy92806]

---

@calibra wrote:

@hemangd 

Of course it is only to show that the type of clock driver only depends on the RTL code and not on the timing constraints as you said on previous post.

---

To calibra,

Does it mean you disagree with hemanged?

Let's say you have a global clock pin called, g_clock, and in the pin_constraint, you specify that g_clock is connected to the external clock pin, how can the synthesis tool not doing what you want?

[andy92806]

---

@hemangd wrote:

@andy92806 

>>I mean how does the synthesis tools determines where to route the clock to each module?  How does the synthesis tool make sure the clock comes from the main tree and not from an output of a flip-flop?

It is not recommended to forward the clock from a flops output. 

Once you define a clock as an input port in your entity you will have to write a create_clock constraint as well for that clock name and need to specify a GC pin related to it so the tool will understand that yes this is the clock and will use dedicated routing for your clock and it will not use fabric routing for the same. 

Based on your clock constraints tool will understand that whether to take that signal as clock routing (dedicated routing).

---

To hemangd,

Since the physical clock pin will be buffered internally, can you physically have a pin that is connected to the clock pin?  I mean most likely the input clock pin will be connected to the clock tree through a series of buffers right?

[hemangd · Accepted solution]

@andy92806 

>>can you physically have a pin that is connected to the clock pin? 

Yes, the FPGA device has GCIO pins for clocks. You may check it in pin planning or its datasheet. 

>> I mean most likely the input clock pin will be connected to the clock tree through a series of buffers right? 

Yes, it will be global buffers like BUFGCE etc. 

If you have some time then you can go through the clocking architecture and CLB architecture UGs (User Guides/datasheet)  for a specific Xilinx FPGA device to understand better on these global routing and fabric routing. 

Also, have a look into this thread to understand other ways to divide a clock https://forums.xilinx.com/t5/Implementation/Deriving-a-slow-clock/m-p/672350#M14258