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Contributor
Contributor
3,863 Views
Registered: ‎12-29-2009

How to make the Post_Route Simulation work?

hello,fellows.

        I have got the right results in the behavioral simulation. When I download the stream into the chip, I can not get the same outputs as the behavioral simulation.

Furthermore,it takes more then ten minutes for the post_route simulation. However,the post_route simulation give out nothing. Because the process of P_R simulation is still running,you can not close the ISE.  

      My software is ISE10.1.3. Is there anyone who encounter the similar problem?

Please give me a solution.

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Historian
Historian
3,851 Views
Registered: ‎02-25-2008

I often see behavioral simulations that are nothing more than just toggling a few bits to see what comes out. That's not a simulation. You need models of your inputs and outputs. The input models generate proper stimulus, and the output models test for expected results.

----------------------------Yes, I do this for a living.
Xilinx Employee
Xilinx Employee
3,819 Views
Registered: ‎08-02-2007

If you want to do a post route simulation, some files are needed

After clock "simulate post route simulation model" ISE will generate xx.timesim.v/vhd and sdf files

These files will be located in /netgen/post par

please firstly make sure these files excits

If these files are available, you can also launch modelsim stand alone and run the tdo file generated by ISE and see what happened

 

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Contributor
Contributor
3,774 Views
Registered: ‎12-29-2009

I just find the \netgen\par,but there is no post par.

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