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Adventurer
Adventurer
3,013 Views
Registered: ‎12-05-2011

How to run some test-benches in implemented design on Xilinx FPGAs

Hi, 

I need some guidance about running test-benches in some circuits which I have changed their NCD file to a modified one. Then generate .bit by bitgen command. In these new circuits some extra out(in) pins have been added. I want to run random test-benches after that save their outputs. How can I do that? Please give me some advices.

TNX.

--xana
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1 Reply
Teacher eilert
Teacher
2,992 Views
Registered: ‎08-14-2007

Re: How to run some test-benches in implemented design on Xilinx FPGAs

Hi,

how did you do the changes?

Was it done directly on the Netlist, e.g. withthe fpga_editor?

 

In any way, you need to find out about the new pins name. This should appear in the DUTs port map.

You find this when you look at the entity/module port list of the generated HDL Netlist for your post-par simulation.

 

You can write some scripts for automatic string replacement, either in your testbenches or in the simulation netlist to ease up the task of manipulating the port lists.

 

Have a nice simulation

  Eilert

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