07-16-2013 02:32 PM - edited 07-17-2013 09:56 AM
I have the following verilog code:
`timescale 1ns / 1ps module top( ); reg clk = 1;
always #1.25 clk <= ~clk; wire temp; //wire temp2; // added later
assign temp = clk; //assign temp2 = clk; //added later
When I simulate this, I see "CLK" as expected but "temp" just has the value 1 and no waveform. When I uncomment the lines marked as "//added later", I can see "CLK" and "temp2" waveforms as expected. But "temp" is still stuck at 1 and there's not waveform for it.
Then I commented the lines marked as "//added later" again and there's not waveform for "temp". Then I renamed "temp" to "temp2" and simulated. This time I could see "CLK" and "temp2" waveforms in the simulation window toggling as expected.
It could be that I'm just not seeing the waveforms. For example in the first scenario, I'm just seeing a "1" and no waveform. There are also some other signals that when added to the wave window don't show a waveform. How can I enable the waveform?
07-17-2013 10:57 AM
07-17-2013 08:22 AM
Assigning the clock to a wire seemed to work with me, although I set up my clock stimulus slightly differently.
I used an always construct, as you did, but I contained it to a module, then assigned outside the module. Here is an example
// Note: CLK must be defined as a reg when using this method
parameter PERIOD = <value>;
CLK = 1'b0;
#(PERIOD/2) CLK = 1'b1;
assign temp = CLK;
07-17-2013 10:47 AM
I tried using a separate module for clock generation as you suggested. In my top level module I instantiate two clocks "CLK_20MHz" and "CLK_25MHz". When I simulate I can see the waveform of both clocks. Then, from the clock module, I add the register "CLK". However, I see no waveforms for "CLK". But when I add "$monitor("%d,\t%b",$time, CLK);" inside the clock module, I can see in the logs that "CLK" is actually toggling as expected. I don't know why the simulation window doesn't show the waveform? And how I can show/enable the waveform?
07-17-2013 10:57 AM
07-29-2015 09:05 PM