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Observer
Observer
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Registered: ‎02-11-2016

How to simulate OSERDESE3 with VCS?

Hi,

VCS compile passed but reports below warning when elab. Not sure how to fix it. 

-- Warn: /path/to/Xilinx/Vivado/2018.2/data/vhdl/src/unisims/secureip/OSERDESE3.vhd(325): Failed to find the entity OSERDESE3_INST.unisim is in instantiated statement (SIP_OSERDESE3_K2).

In RTL, I include libraries and instantiate OSERDESE3 as below.

library unisim;
use unisim.vpkg.all;
use unisim.vcomponents.all;
library secureip;
use secureip.all;

...

-- OSERDESE3: Output SERial/DESerializer
-- UltraScale
-- Xilinx HDL Language Template, version 2018.2
i_OSERDESE3 : OSERDESE3
generic map(
DATA_WIDTH => 4, --ParallelDataWidth(4-8)
INIT => '0', --Initialization value of the OSERDES flip-flops
IS_CLKDIV_INVERTED => '0', --Optional inversion for CLKDIV
IS_CLK_INVERTED => '0', --Optional inversion for CLK
IS_RST_INVERTED => '1', --Optional inversion for RST
SIM_DEVICE => "ULTRASCALE"--Set the device version (ULTRASCALE,ULTRASCALE_PLUS,ULTRASCALE_PLUS_ES1,ULTRASCALE_PLUS_ES2)
)
port map (
OQ => ser_4_out(i), --1-bit output: Serial Output Data
T_OUT => open, --1-bit output: 3-state control output to IOB
CLK => clk_640, --1-bit input: High-speed clock
CLKDIV => clk_160, --1-bit input: Divided Clock
D => oserdes_in((i+1)*8-1 downto i*8), --8-bit input: Parallel DataInput
RST => resetn_640, --1-bit input: Asynchronous Reset
T => '0' --1-bit input: Tristate input from fabric
);

Vivado Version: 2018.2

Target Device: VCU108, VU095

Xilinx libraries are compiled with Vivado GUI tcl commands:

config_compile_simlib -cfgopt {vcs_mx.vhdl.unisim:-nc -kdb}

config_compile_simlib -simulator vcs_mx

compile_simlib -simulator vcs_mx -family virtexu -library unisim -language vhdl -directory ./lib

From compile_simlib.log, unisim and secureip are sucessfully compiled.

compile_simlib: 0 error(s), 0 warning(s), 100.00 % complete

***********************************************************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: vcs_mx *
* Compiled on: Wed Feb 19 09:42:03 2020 *
* *
***********************************************************************************************************************
* Library | Language | Mapped Library Name | Error(s) | Warning(s) *
*---------------------------------------------------------------------------------------------------------------------*
* secureip | verilog | secureip | 0 | 0 *
*---------------------------------------------------------------------------------------------------------------------*
* unisim | vhdl | unisim | 0 | 0 *
*---------------------------------------------------------------------------------------------------------------------*

Also add unisim and secureip to synopsys_sim.setup.

unisim > unisim
unisim : ../../../fpga/src/xilinx/lib/unisim

secureip > secureip
secureip : ../../../fpga/src/xilinx/lib/secureip

Thanks!

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