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Observer
Observer
7,798 Views
Registered: ‎11-19-2007

How to simulate black box & coregen

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Hi,

I'm using Xilinx ISE Foundation to modify and simulate a design. The design has xilinx component primitives such as IBUFG, CLKDLL and two blockram generated by coregen.

However, I can simulate the components mentioned above. The log tells me that something like: "ibufg remains a black-box since it has no binding entity"

Looking at the Xilinx Syn & Sim guide, there are 5 types of simulation:
1. RTL
2. Post-synthesis gate level simulation (preNGD build)
3. Post-synthesis gate level simulation (postNGD build)
4. Post-map partial timing
5. Timing simulation post place and route.

I assume have to do a no2. or no3. How do i do that?

Or do i just have to add some libraries to the top level file or to the test bench file?

If i am completely missing the point, please educate me. I'm all eyes.

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Xilinx Employee
Xilinx Employee
9,250 Views
Registered: ‎08-15-2007

Re: How to simulate black box & coregen

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Have you included the following lines in your source code in order to refer to the Unisims library?

 

Library UNISIM;
use UNISIM.vcomponents.all;

 

You must add these lines on any source code that instantiate primitives from the UNISIM library (IBUFG, DCM, etc.)

 

If you are still interested in running Post-Synthesis simulations, you'll need to:

 

1) Run "Generate Post-Synthesis Simulation Model" under the XST sub-processes.

2) An automated simulation flow for post-synthesis simulation is not available via ISE.  You'll need to run the simulation via ISim standalone.  To do so, refer to the ISim Help (refer to sticky thread about ISim documentation) to learn how to setup a project file, run the HDL compiler (fuse), and run ISim standalone.

 

As bassman earlier stated, keep in mind that though this is a good practice, it is not a required practice.  That is, if you are interested to verify functionality post synthesis, you may be interested in simply running a Post-Place and Route simulation (this flow can be launched directly from ISE).

 

Hope this helps.

 

Eddie

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Historian
Historian
7,781 Views
Registered: ‎02-25-2008

Re: How to simulate black box & coregen

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icel wrote:
Hi,

I'm using Xilinx ISE Foundation to modify and simulate a design. The design has xilinx component primitives such as IBUFG, CLKDLL and two blockram generated by coregen.

However, I can simulate the components mentioned above. The log tells me that something like: "ibufg remains a black-box since it has no binding entity"

Looking at the Xilinx Syn & Sim guide, there are 5 types of simulation:
1. RTL
2. Post-synthesis gate level simulation (preNGD build)
3. Post-synthesis gate level simulation (postNGD build)
4. Post-map partial timing
5. Timing simulation post place and route.

I assume have to do a no2. or no3. How do i do that?

Or do i just have to add some libraries to the top level file or to the test bench file?

If i am completely missing the point, please educate me. I'm all eyes.


 

Why do you need to do post-synthesis simulations?

 

-a

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
7,773 Views
Registered: ‎08-15-2007

Re: How to simulate black box & coregen

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Hello,

 

To address bassman's question, each simulation point offers some help in debugging a design.  Post-Synthesis simulation helps validate the synthesized netlist.  If the netlist passes verification at this point, any changes to design functionality would be attributed to the implementation tools, not the synthesizer.  In all, it's always a good debugging practice to validate your design netlist at each of the key steps of the implementation process.

 

icel, the errors you are encountering are probably due to the fact that you are using primitives from the UNISIM library, but have either yet to pre-compile them, or reference the library in your source code.  Before I recommend anything, can you answer these questions?

 

1) Which simulator are you using (ISE Simulator, ModelSim, another 3rd party simulator?)

2) Are you coding in VHDL or Verilog?

3) If using a simulator other than ISE Simulator or ModelSim XE, have you ran the Simulation Libraries Compilation Wizard in order to pre-compile the libraries?

 

 

 

Eddie
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Observer
Observer
7,739 Views
Registered: ‎11-19-2007

Re: How to simulate black box & coregen

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1) I'm using ISE Simulatior

2) VHDL

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Xilinx Employee
Xilinx Employee
9,251 Views
Registered: ‎08-15-2007

Re: How to simulate black box & coregen

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Have you included the following lines in your source code in order to refer to the Unisims library?

 

Library UNISIM;
use UNISIM.vcomponents.all;

 

You must add these lines on any source code that instantiate primitives from the UNISIM library (IBUFG, DCM, etc.)

 

If you are still interested in running Post-Synthesis simulations, you'll need to:

 

1) Run "Generate Post-Synthesis Simulation Model" under the XST sub-processes.

2) An automated simulation flow for post-synthesis simulation is not available via ISE.  You'll need to run the simulation via ISim standalone.  To do so, refer to the ISim Help (refer to sticky thread about ISim documentation) to learn how to setup a project file, run the HDL compiler (fuse), and run ISim standalone.

 

As bassman earlier stated, keep in mind that though this is a good practice, it is not a required practice.  That is, if you are interested to verify functionality post synthesis, you may be interested in simply running a Post-Place and Route simulation (this flow can be launched directly from ISE).

 

Hope this helps.

 

Eddie

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Observer
Observer
7,718 Views
Registered: ‎11-19-2007

Re: How to simulate black box & coregen

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Hi,

 

I've added the unisim libraries to the design. It seems to be working fine. The simulation log doesnt show any black box instantiation issue anymore.

Thanks for all the advice.

 

icel

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