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Contributor
Contributor
4,164 Views
Registered: ‎11-02-2009

How to simulate using the "ADDSUB_MACRO" and "MULT_MACRO" ?

Hi,

I need to simulate a piece of VHDL code using the MULT_MACRO and ADDSUB_MACRO.

These are the macro for the virtex5.

 

When I run the modelsim, it said that do not recognize these macro.  I added the library "unimacro" but seems that I have something wrong because did not work.

 

Anyone who can help me? Some tips...?

 

Thanks in advance

Omar

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3 Replies
Advisor evgenis1
Advisor
4,150 Views
Registered: ‎12-03-2007

Re: How to simulate using the "ADDSUB_MACRO" and "MULT_MACRO" ?

Hi,

 

Those macros reference modules in unisims library. Make sure you add it as well. If that doesn't help, try referencing individual modules that modelsim doesn't find. Sources are in ISE installation under /vhdl/src/unisims/primitive

 

 

Hope that helps,

OutputLogic 

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Xilinx Employee
Xilinx Employee
4,138 Views
Registered: ‎08-02-2007

Re: How to simulate using the "ADDSUB_MACRO" and "MULT_MACRO" ?

These files should be compiled into unisim by Compxlib

If not , please refer to source file in  C:\Xilinx\12.1\ISE_DS\ISE\vhdl\src\unimacro

You can compile these source files into t he project

 

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Xilinx Employee
Xilinx Employee
4,121 Views
Registered: ‎11-28-2007

Re: How to simulate using the "ADDSUB_MACRO" and "MULT_MACRO" ?

In 12.1, they are in unimacro library (see attached snapshot of modelsim library browser). If you already compiled all simulation libraries and don't see the "unimacro" library in your modelsim library browser, you will need to map the library.

 

 

Cheers,
Jim
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