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Adventurer
Adventurer
4,122 Views
Registered: ‎04-18-2015

How to test an IEEE 754 standard floating point adder

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Hi,

 

Firstly, I tested this adder with special cases such as 0, +/- infinity and not number.

Secondly, I tested it with random inputs combinations.

 

What else can I do to test the design fully?

 

Best wishes,

Lei Xun

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Voyager
Voyager
6,229 Views
Registered: ‎04-21-2014

In general.

 

1.  Exhaustive if possible. (not likely in this case).

2.  Identify all boundary conditions, and test those.

3.  Look for third party test vectors.

4.  Synthesizable testbench comparing two different independently developed solutions at wire speed.  (useful to the extent it finds discrepancies).  If you test in hardware you'll be able to test a lot more vectors.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

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Scholar
Scholar
4,116 Views
Registered: ‎02-27-2008

d,

 

First, why are you doing this?

 

Second, other than random samples, there is a full exhaustive test of all numbers.  I am sure you realize that would take a long time, so it is not useful.

 

How we test before we ship to guarantee operation is not something we share.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Voyager
Voyager
6,230 Views
Registered: ‎04-21-2014

In general.

 

1.  Exhaustive if possible. (not likely in this case).

2.  Identify all boundary conditions, and test those.

3.  Look for third party test vectors.

4.  Synthesizable testbench comparing two different independently developed solutions at wire speed.  (useful to the extent it finds discrepancies).  If you test in hardware you'll be able to test a lot more vectors.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

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Xilinx Employee
Xilinx Employee
4,074 Views
Registered: ‎08-01-2008

Are you using xilinx floating point IP
https://www.xilinx.com/support/documentation/ip_documentation/floating_point/v7_0/pg060-floating-point.pdf

Core provide demo test bench . You can run the simulation and verify results

Thanks and Regards
Balkrishan
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