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Contributor
Contributor
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Registered: ‎05-29-2018

How to trig re-simulate on HDL

Dear,

I would like to trigger the timing re-simulate on HDL (verilog/SystemVerilog).
In the initial of simulation related to ethernet/network, I run the function with DPI-C to catch the tun/tap interface,
but, when I run re-simulation botton, the process(using tun/tap interface) is alive, so failed to catch the interface.

To solve this, I want to trigger the time when the timing resimulation is executed, then I want to abort the process.

Anybody know how to do this ? or alternative? 

Best Regards
toku1938 

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