UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
657 Views
Registered: ‎02-16-2018

How to turn off VCD file dump during simulation?

Hi All,

I am simulating design in batch mode. Can someone tell me how to turn off default VCD file dump in Vivado Simulator? I need to do this due to disk space constraints.

Thank you.

0 Kudos
1 Reply
Moderator
Moderator
593 Views
Registered: ‎09-15-2016

Re: How to turn off VCD file dump during simulation?

Hi @shriniket_ssrlabs,

 

You may try using stop_vcd command to stop capturing VCD output (equivalent of $dumpoff verilog system task).

 

For more information please refer the below user guide page#120

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug900-vivado-logic-simulation.pdf

 

Just incase if you want to limit the size you can try using limit_vcd command this will limit the maximum size of the VCD file on disk (equivalent of $dumplimit verilog task) as mentioned in below user guide:

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug835-vivado-tcl-commands.pdf

 

Hope this helps.

 

Thanks & Regards,

Sravanthi B

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos