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Explorer
Explorer
2,346 Views
Registered: ‎05-22-2008

How to use IP Core simulation sources

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I have a design in Vivado 2018.1 wherein, among other blocks of vhdl and Xilinx IP cores, I have created and instantiated a Xilinx FFT core. I've got testbeds written and included for both my top level and most of my subcomponents.

 

When I create FFT core from the IP catalog, it creates a bunch of files, and on the IP Sources tab of the Sources window, under simulation there are 4 files, one of which is tb_xfft_0.vhd. 

 

This file appears to be a testbed for the xfft_o core I just created. How do I run this tb in the simulator? This file doesn't show up in my design hierarchy in the Hierarchy window. As far as I can tell with vivado simulator, one has to set whatever file to top before pressing run simulation. I suppose I could create a copy of this file, rename it and manually add as a simulation source, but that can't be the right answer.

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Moderator
Moderator
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Registered: ‎03-16-2017

Hi @mckinjo4,

 

In simulation sources, you need to click on the arrow of the xfft_0.xci. Then it will open IP's hierarchy. 

 

Then you can right click on the testbench and set it as top. 

 

tbbb.JPG

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi @mckinjo4,

 

After adding the FFT core from IP catalog, generate the output products it will lead to creation of simulation models for the IP.

After that set the tb_fft_0 as a top module and proceed for simulation.

 

Please check this forum link:

https://forums.xilinx.com/t5/Simulation-and-Verification/How-to-generate-demonstration-testbench-for-LogiCORE-FFT-IP-in/td-p/733841

 

Thanks,

Raj.

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Explorer
Explorer
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Registered: ‎05-22-2008

Right, I generate output products, and Vivado created the testbench, like I said in my original post. But the testbench isn't shown in the Hierarchy Tab; it is only shown in the IP Sources Tab; and when I right click on it, the only options that are not grey'ed out are:

 

Source File Properties, Open File, Report IP Status, Copy All files into Project, Disable File, Set Used in, Edit constraint sets, Edit Simulation sets, Add Sources.

 

The option to "Set at Top" is neither greyed out, nor there at all.

IMG_20181003_145042_down.jpg

 

 

IMG_20181003_145056_down.jpg

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Moderator
Moderator
2,306 Views
Registered: ‎03-16-2017

Hi @mckinjo4,

 

In simulation sources, you need to click on the arrow of the xfft_0.xci. Then it will open IP's hierarchy. 

 

Then you can right click on the testbench and set it as top. 

 

tbbb.JPG

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

View solution in original post

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Explorer
Explorer
2,300 Views
Registered: ‎05-22-2008

Duh. That worked. I don't know how I missed that. Thank you so much.

 

It's weird that as a TB it's under the core in the hierarchy, is there a way to do that with custom vhd files; to make my module_tb.vhd live underneath my module.vhd?

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