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Registered: ‎09-15-2019

How to view boolean logic optimized pre-synthesis netlist in Vivado 2019.1

I have been using the Xilinx ISE tools for years and I recently switched to Vivado. In the ISE tools, I could view the optimized netlist, before it had been mapped onto the target architecture. Now, with Vivado, I can see the unoptimized RTL schematic or the post-synthesis schematic, but I haven't found a way of viewing the boolean logic optimized netlist. Is there any way of doing this in Vivado 2019.1?



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Registered: ‎07-09-2009

welcome to Vivado, its very different to ISE...

I can't remember seeing a netlist in vivado, schematics are the best you get,

Vivado is aimed at the ASIC crowd , few design starts, many people working on one project, Personally I'm involved mainly in the other sort of projects, many starts / experiments, few people, ISE worked just great for us.

With vivado you will spend much more time up front defining timing constraints, including cross clock constraints, vivado assumes all clocks need to be timed to each other, unless you say otherwise.

The tool will stop working once it has met your constraints , so no constraints, you will get less than optimum results.
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