10-21-2019 10:06 AM
I have been using the Xilinx ISE tools for years and I recently switched to Vivado. In the ISE tools, I could view the optimized netlist, before it had been mapped onto the target architecture. Now, with Vivado, I can see the unoptimized RTL schematic or the post-synthesis schematic, but I haven't found a way of viewing the boolean logic optimized netlist. Is there any way of doing this in Vivado 2019.1?
Thanks,
jdb2
10-21-2019 10:39 AM