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Explorer
Explorer
2,881 Views
Registered: ‎08-14-2007

How to write smart testbench for LVDS _n signals in verilog?

Hi there,

 

I need to generate testbench for LVDS signals.

 

I'm tired of assigning XX_n signals everytime when I need to assign XX signal.

 

Is there a smart way to generate XX_n signals automatically with the state of XX signal?

 

Thank you very much.

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1 Reply
Historian
Historian
2,878 Views
Registered: ‎02-25-2008

Re: How to write smart testbench for LVDS _n signals in verilog?

 


@unicorn70 wrote:

Hi there,

 

I need to generate testbench for LVDS signals.

 

I'm tired of assigning XX_n signals everytime when I need to assign XX signal.

 

Is there a smart way to generate XX_n signals automatically with the state of XX signal?

 

Thank you very much.


I just use the Xilinx OBUFDS in the testbench.

 

----------------------------Yes, I do this for a living.
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