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Contributor
Contributor
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Registered: ‎03-28-2015

How to write the value of signal in signed decimal or hexadecimal formate in a file using verilog or vhdl.

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I want to write the value of a signal in signed decimal or hexadecimal formate using verilog or vhdl in file for verifying it in matlab. so any one help me in this regard.. thanks

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Xilinx Employee
Xilinx Employee
14,929 Views
Registered: ‎09-13-2014

Re: How to write the value of signal in signed decimal or hexadecimal formate in a file using verilog or vhdl.

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if you are using Verilog, you can use system functions like below in example

_____________

module top();

reg [3:0] r1;

integer ch;

initial

begin

    r1 = 4'b1010;

   ch = $fopen("abc", "w");

   $fdisplay(ch, " r1 = %b\n", r1);

    $fdisplay(ch, " r1 = %h\n", r1);

    $fdisplay(ch, " r1 = %d\n", r1); // use this for signed decimal

    $fdisplay(ch, " r1 = %o\n", r1);

    $fclose(ch);

end

endmodule

_______________

 

For VHDL, you can have something like this

___________

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use std.textio.all;

entity top is

end entity top;

 

architecture arch of top is

signal s1 : unsigned(0 to 3) := (others => '1');

begin

process

variable sttr : line;

file dataout : text open write_mode is "abc";

begin

    write(sttr, to_integer(s1));

   writeline(dataout, sttr);

    wait;

end process;

end;

________

 

--dhiRAj

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Xilinx Employee
Xilinx Employee
8,335 Views
Registered: ‎06-14-2012

Re: How to write the value of signal in signed decimal or hexadecimal formate in a file using verilog or vhdl.

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Do you mean in the testbench or during simulation?

 

Regards

Sikta

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Xilinx Employee
Xilinx Employee
14,930 Views
Registered: ‎09-13-2014

Re: How to write the value of signal in signed decimal or hexadecimal formate in a file using verilog or vhdl.

Jump to solution

if you are using Verilog, you can use system functions like below in example

_____________

module top();

reg [3:0] r1;

integer ch;

initial

begin

    r1 = 4'b1010;

   ch = $fopen("abc", "w");

   $fdisplay(ch, " r1 = %b\n", r1);

    $fdisplay(ch, " r1 = %h\n", r1);

    $fdisplay(ch, " r1 = %d\n", r1); // use this for signed decimal

    $fdisplay(ch, " r1 = %o\n", r1);

    $fclose(ch);

end

endmodule

_______________

 

For VHDL, you can have something like this

___________

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use std.textio.all;

entity top is

end entity top;

 

architecture arch of top is

signal s1 : unsigned(0 to 3) := (others => '1');

begin

process

variable sttr : line;

file dataout : text open write_mode is "abc";

begin

    write(sttr, to_integer(s1));

   writeline(dataout, sttr);

    wait;

end process;

end;

________

 

--dhiRAj

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Contributor
Contributor
8,297 Views
Registered: ‎03-28-2015

Re: How to write the value of signal in signed decimal or hexadecimal formate in a file using verilog or vhdl.

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In test bench.

 

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Xilinx Employee
Xilinx Employee
8,290 Views
Registered: ‎09-13-2014

Re: How to write the value of signal in signed decimal or hexadecimal formate in a file using verilog or vhdl.

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Yes in testbench or is design unit where the signals are declared.

 

 

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