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Visitor
Visitor
8,352 Views
Registered: ‎09-23-2015

I produce a HDL functional model from a schematic file, and it shows "BLACK_BOX"!!!

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The schematic file is attached below. All the components(AND3B2, AND3B1, AND3) are chosen from the libraries which were automatically installed. After composing the schematic file, I produce the HDL functional model, but it shows “attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";”. “attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";” “attribute BOX_TYPE of AND3 : component is "BLACK_BOX";” library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity ymq2 is port ( A : in std_logic_vector (1 downto 0); en : in std_logic; Q : out std_logic_vector (3 downto 0)); end ymq2; architecture BEHAVIORAL of ymq2 is attribute BOX_TYPE : string ; component AND3B2 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
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Xilinx Employee
Xilinx Employee
16,051 Views
Registered: ‎08-01-2008
check this ARS

http://www.xilinx.com/support/answers/9838.html
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
8,350 Views
Registered: ‎08-01-2008
what is the issue it should be fine . Are you not getting expected results .

No attachment with post!
Thanks and Regards
Balkrishan
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Visitor
Visitor
8,346 Views
Registered: ‎09-23-2015
Schematic picture is here!
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Visitor
Visitor
8,344 Views
Registered: ‎09-23-2015
Sorry, I cannot post the attachments.........I don't know what is wrong.......I'm wondering why are the components are "black". Should I write the behaviral architecture for the components?
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Xilinx Employee
Xilinx Employee
16,052 Views
Registered: ‎08-01-2008
check this ARS

http://www.xilinx.com/support/answers/9838.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
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Visitor
Visitor
8,321 Views
Registered: ‎09-23-2015
Thx for your answer! A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format. So in my case, the components are not created by HDL code. I just don't need to care about it!
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