The schematic file is attached below. All the components(AND3B2, AND3B1, AND3) are chosen from the libraries which were automatically installed. After composing the schematic file, I produce the HDL functional model, but it shows “attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";”. “attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";” “attribute BOX_TYPE of AND3 : component is "BLACK_BOX";”
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity ymq2 is
port ( A : in std_logic_vector (1 downto 0);
en : in std_logic;
Q : out std_logic_vector (3 downto 0));
end ymq2;
architecture BEHAVIORAL of ymq2 is
attribute BOX_TYPE : string ;
component AND3B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
begin
XLXI_1 : AND3B2
port map (I0=>A(0),
I1=>A(1),
I2=>en,
O=>Q(0));
XLXI_2 : AND3
port map (I0=>A(0),
I1=>A(1),
I2=>en,
O=>Q(3));
XLXI_5 : AND3B1
port map (I0=>A(0),
I1=>A(1),
I2=>en,
O=>Q(1));
XLXI_6 : AND3B1
port map (I0=>A(0),
I1=>A(1),
I2=>en,
O=>Q(2));
end BEHAVIORAL;
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