UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor malarkey1989
Visitor
8,359 Views
Registered: ‎09-23-2015

I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution

The schematic file is attached below. All the components(AND3B2, AND3B1, AND3) are chosen from the libraries which were automatically installed. After composing the schematic file, I produce the HDL functional model, but it shows “attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";”. “attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";” “attribute BOX_TYPE of AND3 : component is "BLACK_BOX";”

 

 

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

 

entity ymq2 is

   port ( A  : in    std_logic_vector (1 downto 0);

          en : in    std_logic;

          Q  : out   std_logic_vector (3 downto 0));

end ymq2;

 

architecture BEHAVIORAL of ymq2 is

   attribute BOX_TYPE   : string ;

   component AND3B2

      port ( I0 : in    std_logic;

             I1 : in    std_logic;

             I2 : in    std_logic;

             O  : out   std_logic);

   end component;

   attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";

  

   component AND3

      port ( I0 : in    std_logic;

             I1 : in    std_logic;

             I2 : in    std_logic;

             O  : out   std_logic);

   end component;

   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";

  

   component AND3B1

      port ( I0 : in    std_logic;

             I1 : in    std_logic;

             I2 : in    std_logic;

             O  : out   std_logic);

   end component;

   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";

  

begin

   XLXI_1 : AND3B2

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(0));

  

   XLXI_2 : AND3

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(3));

  

   XLXI_5 : AND3B1

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(1));

  

   XLXI_6 : AND3B1

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(2));

  

end BEHAVIORAL;

 

p.png

0 Kudos
1 Solution

Accepted Solutions
Scholar drjohnsmith
Scholar
16,073 Views
Registered: ‎07-09-2009

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution

Ok, so you want schematics of gates. good luck. 

 

So your question , why black box's 

 

If I remember, and it is going back 20 odd years,

     gates are macros / known code to the synthesiser,

          so when the synthesiser sees these , it does not need to do any work, it can 'just' drop them in.

 

thesimulator as well needs to know what these box's are, 

    but if your using th Xilinx simulator , then its built in,

 

I love using schematics, BUT for top level blocks, 

     coding using gates is goign to get REAL big and messy real quick.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

0 Kudos
6 Replies
Scholar drjohnsmith
Scholar
8,351 Views
Registered: ‎07-09-2009

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution

Only one question

 

WHY schematic ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Visitor malarkey1989
Visitor
8,342 Views
Registered: ‎09-23-2015

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution
I think the schematic design is more convenient to create the top module than the HDL codes.
0 Kudos
Scholar drjohnsmith
Scholar
16,074 Views
Registered: ‎07-09-2009

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution

Ok, so you want schematics of gates. good luck. 

 

So your question , why black box's 

 

If I remember, and it is going back 20 odd years,

     gates are macros / known code to the synthesiser,

          so when the synthesiser sees these , it does not need to do any work, it can 'just' drop them in.

 

thesimulator as well needs to know what these box's are, 

    but if your using th Xilinx simulator , then its built in,

 

I love using schematics, BUT for top level blocks, 

     coding using gates is goign to get REAL big and messy real quick.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

0 Kudos
Moderator
Moderator
8,329 Views
Registered: ‎04-17-2011

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution
@malarkey1989 : Please avoid posting multiple topics with same issue and content. The duplicate one is
https://forums.xilinx.com/t5/Simulation-and-Verification/I-produce-a-HDL-functional-model-from-a-schematic-file-and-it/td-p/656328

Thanks.

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Visitor malarkey1989
Visitor
8,287 Views
Registered: ‎09-23-2015

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution

Thank you sincerely!!!

0 Kudos
Highlighted
Visitor malarkey1989
Visitor
8,283 Views
Registered: ‎09-23-2015

Re: I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

Jump to solution

I'm really sorry. At first, I post one topic, but I don't know where I can find it. So I had to post it again. Please tell me where I can find all the topics I have posted. Thank you very much!

0 Kudos