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Visitor
Visitor
8,463 Views
Registered: ‎09-23-2015

I produced a HDL functional model from a schematic file, and it shows "BLACK_BOX"

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The schematic file is attached below. All the components(AND3B2, AND3B1, AND3) are chosen from the libraries which were automatically installed. After composing the schematic file, I produce the HDL functional model, but it shows “attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";”. “attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";” “attribute BOX_TYPE of AND3 : component is "BLACK_BOX";”

 

 

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

 

entity ymq2 is

   port ( A  : in    std_logic_vector (1 downto 0);

          en : in    std_logic;

          Q  : out   std_logic_vector (3 downto 0));

end ymq2;

 

architecture BEHAVIORAL of ymq2 is

   attribute BOX_TYPE   : string ;

   component AND3B2

      port ( I0 : in    std_logic;

             I1 : in    std_logic;

             I2 : in    std_logic;

             O  : out   std_logic);

   end component;

   attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";

  

   component AND3

      port ( I0 : in    std_logic;

             I1 : in    std_logic;

             I2 : in    std_logic;

             O  : out   std_logic);

   end component;

   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";

  

   component AND3B1

      port ( I0 : in    std_logic;

             I1 : in    std_logic;

             I2 : in    std_logic;

             O  : out   std_logic);

   end component;

   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";

  

begin

   XLXI_1 : AND3B2

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(0));

  

   XLXI_2 : AND3

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(3));

  

   XLXI_5 : AND3B1

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(1));

  

   XLXI_6 : AND3B1

      port map (I0=>A(0),

                I1=>A(1),

                I2=>en,

                O=>Q(2));

  

end BEHAVIORAL;

 

p.png

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Teacher
Teacher
16,177 Views
Registered: ‎07-09-2009

Ok, so you want schematics of gates. good luck. 

 

So your question , why black box's 

 

If I remember, and it is going back 20 odd years,

     gates are macros / known code to the synthesiser,

          so when the synthesiser sees these , it does not need to do any work, it can 'just' drop them in.

 

thesimulator as well needs to know what these box's are, 

    but if your using th Xilinx simulator , then its built in,

 

I love using schematics, BUT for top level blocks, 

     coding using gates is goign to get REAL big and messy real quick.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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6 Replies
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Teacher
Teacher
8,455 Views
Registered: ‎07-09-2009

Only one question

 

WHY schematic ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor
Visitor
8,446 Views
Registered: ‎09-23-2015
I think the schematic design is more convenient to create the top module than the HDL codes.
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Highlighted
Teacher
Teacher
16,178 Views
Registered: ‎07-09-2009

Ok, so you want schematics of gates. good luck. 

 

So your question , why black box's 

 

If I remember, and it is going back 20 odd years,

     gates are macros / known code to the synthesiser,

          so when the synthesiser sees these , it does not need to do any work, it can 'just' drop them in.

 

thesimulator as well needs to know what these box's are, 

    but if your using th Xilinx simulator , then its built in,

 

I love using schematics, BUT for top level blocks, 

     coding using gates is goign to get REAL big and messy real quick.

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Moderator
Moderator
8,433 Views
Registered: ‎04-17-2011
@malarkey1989 : Please avoid posting multiple topics with same issue and content. The duplicate one is
https://forums.xilinx.com/t5/Simulation-and-Verification/I-produce-a-HDL-functional-model-from-a-schematic-file-and-it/td-p/656328

Thanks.

Regards,
Debraj
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Visitor
Visitor
8,391 Views
Registered: ‎09-23-2015

Thank you sincerely!!!

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Highlighted
Visitor
Visitor
8,387 Views
Registered: ‎09-23-2015

I'm really sorry. At first, I post one topic, but I don't know where I can find it. So I had to post it again. Please tell me where I can find all the topics I have posted. Thank you very much!

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