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microchip_zhang
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Registered: ‎08-15-2017

I want to ask a question about glbl.v where is needed in simulation?

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sd1.png

I want to simulate in questasim ,and need glbl.v ,where I can find glbl.v ?

what is the function of glbl_v.class shown in above figure ?

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richardhead
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Registered: ‎08-01-2012

This is why I think glbl.v is a terrible solution to a pretty non-existant problem. glbl.v is always local to a library/example, so it could be different in every single place.

The user should be the one to control the reset from the testbench, not the design itself.

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richardhead
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Registered: ‎08-01-2012

glbl.v is Xilinx annoying way of producing a power on reset. It simply produces a 100ns reset. Some blocks expect it to be a top level block and use heirarchical references to get the GSR out. So if you dont have it your sim will simply not work. Its even worse if you want a VHDL testbench as its a real kludge to get hold of it in your VHDL code.

Several libraries have a copy of the code, for example XPM.

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brimdavis
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Registered: ‎04-26-2012

@microchip_zhang  "where I can find glbl.v "

The glbl.v source is located in the Xilinx installation directory, e.g.  C:\Xilinx\Vivado\2018.3\data\verilog\src\glbl.v

The following AR describes how to compile and run a simulation needing glbl.v ; note the dual top level when invoking the simulator

   https://www.xilinx.com/support/answers/1078.html

 

-Brian

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microchip_zhang
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Registered: ‎08-15-2017

thank you ,

and what about the glbl_v.class ?

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brimdavis
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Registered: ‎04-26-2012

@microchip_zhang   " what about the glbl_v.class"

The ISE directory you posted with glbl_v.class appears to be part of the ISE coregen infrastructure that generates IP cores, and to my knowledge has nothing to do with simulation.

In ISE, the glbl.v file location is typically \xilinx\14.7\ISE_DS\ISE\verilog\src\glbl.v

Note: Some of the ISE IP cores might deliver their own glbl.v as part of their example design simulation, but it should be equivalent to the one given above.

-Brian

 

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microchip_zhang
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Registered: ‎08-15-2017

thanks a lot ,

I have notice some example having glbl.v, but that glbl.v occupys the volume is different with

\xilinx\14.7\ISE_DS\ISE\verilog\src\glbl.v,

have you noticed that ?

the function will be different I think.

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richardhead
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Registered: ‎08-01-2012

This is why I think glbl.v is a terrible solution to a pretty non-existant problem. glbl.v is always local to a library/example, so it could be different in every single place.

The user should be the one to control the reset from the testbench, not the design itself.

View solution in original post

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