I am using device PN: XC4VLX100_11FF1513. I have a dedicated clock pin (lvds_25). When i tried simulate this clock in HyperLynx using xilinx model from ISE,The simulation looked very good, while measuring this clock on board the result were very bad.
The frequency is 320Mhz, the clock looked like a triangle in scope. If we lower the frequency to 160Mhz the clock looks like a square.
How come the IBIS result is different from the real life?
What is the BW for Xilinx IBIS model for LVDS in Virtex 4?