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rameital
Visitor
Visitor
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Registered: ‎12-25-2017

IBIS model BW for LVDS output in Virtex 4

Hello,

 

I am using device PN: XC4VLX100_11FF1513. I have a dedicated clock pin (lvds_25). When i tried simulate this clock in HyperLynx using xilinx model from ISE,The simulation looked very good, while measuring this clock on board the result were very bad.

The frequency is 320Mhz, the clock looked like a triangle in scope. If we lower the frequency to 160Mhz the clock looks like a square.

 

How come the IBIS result is different from the real life?

What is the BW for Xilinx IBIS model for LVDS in Virtex 4?

 

Thanks,

 

Meital

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austin
Scholar
Scholar
675 Views
Registered: ‎02-27-2008

m,

 

I suggest you check the bandwidth of your scope and probes.

 

IBIS models are absolutely accurate.  Your technique (or equipment), perhaps no so much.

Austin Lesea
Principal Engineer
Xilinx San Jose
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