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Contributor
Contributor
12,376 Views
Registered: ‎01-14-2015

IP Core simulation in Vivado

Hello Guys,

 

This might look a very basic question, but i am struggling to perform behavioral simulation of video IP cores in Vivado. (e.g. TPG, VDMA, AXI stream to Video out)

 

To start with, I wanted to verify TPG IP core in standalone mode. For that, I created a Vivado project and added TPG IP core in it. I created a port for ACLK, to which I want to pass CLK stimulus through Test bench.

 

As per PG103, Xilinx has provided a demo test bench to verify TPG IP Core. How to use this test bench provided as it is in read-only mode? I have gone through UG900 & UG937, but could not find how to make use of provided demo test bench. Please let me know documents or video sources to understand this procedure.

 

Thanks,

Prathamesh

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-31-2012

Re: IP Core simulation in Vivado

After you generate the core, there is a folder which is generated which has the example test bench and related files.

 

You can add this test bench file to the design and then simulate your design. Let me know if you can't find the files.

Thanks,
Anirudh

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Moderator
Moderator
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Registered: ‎04-17-2011

Re: IP Core simulation in Vivado

To add, if I am correct the simulation files would be in the folder:
project.srcs\sources_1\ip\v_tpg_0\demo_tb ? and tb_v_tpg_0.v is the Top level Testbench file. And, they are not read-only. You can add it to your project and simulate the IP.
Regards,
Debraj
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Contributor
Contributor
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Registered: ‎01-14-2015

Re: IP Core simulation in Vivado

Thanks Anirudh & Debraj for replying.
Yes Debraj you are right. I found demo test bench and tb_v_tpg_0.v at location you mentioned.



I tried following things.

1. Created Project with just TPG IP core in it. And created port for all its input and output.

2. Created wrapper for the design and generated output products.

3. Then i could locate demo test bench at "../project_2/project_2.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0". It was automatically added to Simulation sources under sim_1.

4. I tried running behaviroual simulation, but I think it did not execute demo test bench. Instead it ran simulation for top wrapper. Because when I forced inputs to aclk, aresetn and aclken and run simulation manually it stated showing some output. (TPG was configured in standalone mode for this simulation)

5. Then I set “tb_design_1_v_tpg_0_0” as a top module and tried running simulation but it gave error

ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.tb_design_1_v_tpg_0_0 in library work located at xsim.dir/work.

6. Then I tried adding test bench and other files manually under sim_2 set. But their, it shows '?' against U0-uut.

7. Then i configured TPG for standalone mode, removed its AXI lite port and wrote small test bench for wrapper. (test bench attached). But when i run it, it gives lot of errors in tcl console.

Is it fine to just add single IP core and run simulation or we need some basic design around it??

 

 

 

 

design_tpg_core.png
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Contributor
Contributor
12,291 Views
Registered: ‎01-14-2015

Re: IP Core simulation in Vivado

Thank you guys, 

 

I think now I am able to run simulation for IP cores. Once again thanks for your prompt replies.

 

 

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12,180 Views
Registered: ‎11-23-2015

Re: IP Core simulation in Vivado

Hi prathamesh.pokale

 

I am in the same situation as you were some months ago. I would like to simulate the video IP cores, but I am not able. I have tryed lot of ways... without chance..

 

Could you tell us how did you find the method?

 

Thanks a lot!!

 

Noemí

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