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Visitor
Visitor
27,644 Views
Registered: ‎12-18-2012

IP core Reed Solomon encoder v7.1

 

Hi,

 

I'm using a IP core Reed Solomon encoder in ISE 14.4 and my problem is the input and output of de core are the same in simulation; it's like the signal bypass was always asserted. I tested the inputs and I think it's all ok, here is the core instantiation:

 

inst_cod_ReedSolomon : codReedSolomon
    port map (
        data_in => data_in,
        start => start_in,
        bypass => '0',
        nd => dvalid_in,
        sclr => rst,
        data_out => data_out,
        info => open,
        rdy => dvalid_out,
        rfd => open,
        rffd => open,
        ce => '1',
        clk => clk
    );

 

Someone knows what's happening?

 

Thanks.

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Xilinx Employee
Xilinx Employee
27,639 Views
Registered: ‎08-02-2011

Re: IP core Reed Solomon encoder v7.1

Can you post a screenshot of the simulation (preferably showing all the control signals). 

 

It would also be nice to see your .xco file

www.xilinx.com
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Visitor
Visitor
27,630 Views
Registered: ‎12-18-2012

Re: IP core Reed Solomon encoder v7.1

Hi,

 

Yesterday, I tried it with ip core v8.0 what it has axi protocol and I got a right work, but only with the encoder and decoder in the project. If I join the encoder in the complete project (a system with a few FIFOs, interleaver, deinterleaver and so on) the problem is the same.

Here you have both simulation with all interfaces and screenshot of the .xco.

 

Thanks so much.

 

RS encoder working wrong

RS encoder working right

.xco configuration part 1

.xco configuration part 2

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Newbie
Newbie
27,581 Views
Registered: ‎03-20-2013

Re: IP core Reed Solomon encoder v7.1

he yaar can u please send me the reed solomon decoder ip core with program to my  mail id varadharaj.p@gmail.com 

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