cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dys__8686
Visitor
Visitor
719 Views
Registered: ‎05-29-2021

IP netlist syntax error (Simulate a design that includes an VHDL IP core with Icarus Verilog)

I want to simulate a design that includes an IP core (Multiplier).

The netlist generated by another IP(Block Memory Generator) through the command "write_verilog" can be used.

However the netlist of Multiplier report an error.  (Icarus Verilog only shows 'syntax error. I give up.')

How can I simulate the design that includes the Multiplier with the third simulator?

 

 

 

0 Kudos
11 Replies
drjohnsmith
Teacher
Teacher
710 Views
Registered: ‎07-09-2009

Icarus Verilog is a simulator

   were the cores generated with the Xilinx software ?

If so I bet they contain entities that are included in the xilinx Unisim library

    your going to have to include that into your simulator

 

Any reason your not using the xilinx simulator that s built into the tools,

 

Which xilinx tools are you using and what device you targeting ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
dys__8686
Visitor
Visitor
700 Views
Registered: ‎05-29-2021

Yes,I  generated  the cores with the Vivado,and I have already included the Xilinx library.

I need to use the cocotb to test my project,so I can't using the xilinx simulator that s built into the tools.

My project is implemented on U200.

I also use the post-synthesis to generate the netlist,but still have errors.

dys__8686_0-1622306887994.png

dys__8686_1-1622306916124.png

Thank you!

0 Kudos
drjohnsmith
Teacher
Teacher
669 Views
Registered: ‎07-09-2009

sorry, dont know your simulator

   but its def saying its missing some entities,

 

Suggest you contact your simulators support site.

 

BTW: What is cocotb 

   if its a test bench, then can you not add that to the vivado simulator ?

 

You might get clues here

https://www.xilinx.com/support/answers/1078.htm

This is about how to use modlesim with the xilinx entities, and how to comile the xilinx librares for modelsim,

    Im expecting you will have to compile the xilinx libs into your simulator, something similar,

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
dys__8686
Visitor
Visitor
592 Views
Registered: ‎05-29-2021

Thank you! And I want to confirm a question.

Generally,the VHDL IP  can also be used for simulators that only support verilog through netlist . Is this correct?

I need to use the cocotb for writing the test bench in Python(such as generating packet),but the cocotb doesn't support Vivado.

 

I really appreciate your help .

0 Kudos
richardhead
Scholar
Scholar
562 Views
Registered: ‎08-01-2012

@drjohnsmith cocotb is a python based verification framework for hdls . https://github.com/cocotb/cocotb. I assume it doesn't work with vivado because of the poor vhdl 2008 support and maybe lack of vpi vhpi support?  I don't see it get so many mentions in the vhdl world behind the"big 3" ( osvvm, uvvm and vunit)

@dys__8686 it definitely looks like missing libraries.  Are you sure you have included unisim properly?

drjohnsmith
Teacher
Teacher
519 Views
Registered: ‎07-09-2009

You ask

"Generally,the VHDL IP  can also be used for simulators that only support verilog through netlist"

 

Normally , simulators are sold per language, 

    If the "netlist" is in a language that your simulator supports then all is ok,

  Unisim  and the other xilinx libs will be needed for the xilinx code to work in any simulator,

      you "just" need to "compile" the xilinx libs for your simulator,

  sorry, have chat to your simulator support forum, 

    I've certainly not seen it on the forums before, though a search shows a few posts.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
dys__8686
Visitor
Visitor
413 Views
Registered: ‎05-29-2021

@drjohnsmith @richardhead 

Sorry,I made a mistake.

I thought I can include the lib by "iverilog -y %vivado_dir%/unisims.

Icarus verilog isn't in the available list of simulators for the command "compile_simlib" -simulator switch.

Is there any other way to compile the lib?

0 Kudos
drjohnsmith
Teacher
Teacher
385 Views
Registered: ‎07-09-2009

sounds like you will have to ask icarus how to include packages into there sinulator,

   when you get answer, please get back to us.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
dys__8686
Visitor
Visitor
327 Views
Registered: ‎05-29-2021

I got the answer to solve the firse error.

" If it is using any SystemVerilog features, add the -g2012 option to the iverilog command line. "

However, it report a syntax error on line 186 of IP/mult_gen_1.v. 

Could you give me a few pointers with this problem?  Thank you.

dys__8686_0-1622738551396.png

 

0 Kudos
graces
Moderator
Moderator
300 Views
Registered: ‎07-16-2008

It looks to have trouble with IP encrypted file.

To encrypt IP such that it can be read by a IEEE-1735-2014 V2 compliant third-party tool, you must obtain the public encryption key directly from the third-party tool provider. The third-party key definition must be in the pre-defined format and must be placed within a separate begin_toolblock/end_toolblock pair. During encryption, the Vivado tools use both public keys.

As iverilog is not compatible 3rd party tool with Vivado, I'm afraid it will not work with most IPs.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
dys__8686
Visitor
Visitor
277 Views
Registered: ‎05-29-2021

Oh,I see. I appreciate your help very much.

0 Kudos