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jgregnash
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Registered: ‎02-09-2016

ISE 14.7 iSim: odd error prevents simulation

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I just installed ISE 14.7 W10 version (VirtualBox). I  have a project that successfully passed synthesis and implementation (Virtex-6). Then the test bench passed "Behavioral Check Syntax" in the Simulation tab.  When I try "Simulate Behavioral Model" I get an error:

ERROR:HDLCompiler:303 - "/build/xfndry10/P.20131013/rtf/vhdl/src/std/textio.vhd" Line 35: Character ';' is not in type bit

I don't know what this is (or where it is), since I'm not using textio.vhd at all.   

(Previously, for this project, when running under W10 ISE 14.7 (non-virtual) using PlanAhead, everything worked fine.  My only problem was that I had lots of seemingly random iSim crashes when debugging the circuit.  This is why I installed the "supported" version of ISE 14.7 W10, that runs virtually, so hopefully I'd have no more such crashes.)

Greg

Below is the console output (I've seen posts on glbl.v, so I guess it's needed):

Started : "Simulate Behavioral Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/ise/ise_projects/FFT256/FFT256/tb_isim_beh.exe -prj /home/ise/ise_projects/FFT256/FFT256/tb_beh.prj work.tb work.glbl {}
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/ise/ise_projects/FFT256/FFT256/tb_isim_beh.exe -prj /home/ise/ise_projects/FFT256/FFT256/tb_beh.prj work.tb work.glbl
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files
Analyzing Verilog file "/home/ise/ise_projects/FFT256/FFT256/../project_1/project_1.srcs/sources_1/imports/FFT256/dsp48e1_wrap_rhs.v" into library work
Analyzing Verilog file "/home/ise/ise_projects/FFT256/FFT256/../project_1/project_1.srcs/sources_1/imports/FFT256/dsp48e1_wrap_lhs.v" into library work
Analyzing Verilog file "/home/ise/ise_projects/FFT256/FFT256/../project_1/project_1.srcs/sources_1/imports/FFT256/top.v" into library work
WARNING:HDLCompiler:568 - "/home/ise/ise_projects/FFT256/FFT256/../project_1/project_1.srcs/sources_1/imports/FFT256/top.v" Line 680: Constant value is truncated to fit in <2> bits.
WARNING:HDLCompiler:568 - "/home/ise/ise_projects/FFT256/FFT256/../project_1/project_1.srcs/sources_1/imports/FFT256/top.v" Line 695: Constant value is truncated to fit in <2> bits.
Analyzing Verilog file "/home/ise/ise_projects/FFT256/FFT256/tb.v" into library work
Analyzing Verilog file "/opt/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/Wb14.vhd" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/Wb13.vhd" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/Wb12.vhd" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/Wb11.vhd" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/twd_ROM.vhd" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/norm_cm.vhd" into library work
Parsing VHDL file "/home/ise/ise_projects/FFT256/FFT256/mpe_cm.vhd" into library work
Starting static elaboration
ERROR:HDLCompiler:303 - "/build/xfndry10/P.20131013/rtf/vhdl/src/std/textio.vhd" Line 35: Character ';' is not in type bit
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

Process "Simulate Behavioral Model" failed

 

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bandi
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566 Views
Registered: ‎09-15-2016

Hi @jgregnash ,

Can you please try to clean up the project select Project > Cleanup Project Files or try to build the project from scratch and run simulation again check if you are still facing issues.  Please share the design to check this issue at our end.

Thanks & Regards,
Sravanthi B
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bandi
Moderator
Moderator
567 Views
Registered: ‎09-15-2016

Hi @jgregnash ,

Can you please try to clean up the project select Project > Cleanup Project Files or try to build the project from scratch and run simulation again check if you are still facing issues.  Please share the design to check this issue at our end.

Thanks & Regards,
Sravanthi B
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Give Kudos to a post which you think is helpful and reply oriented.
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jgregnash
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Registered: ‎02-09-2016
Cleanup Project didn't work. After rebuilding from scratch-that worked. I had used a previous PlanAhead directory for my project (at first I had assumed this gui would be available in the W10 version), thinking Navigator wouldn't care. Obviously there was something in that directory corrupting the simulation.-Thanks
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