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Adventurer
Adventurer
4,599 Views
Registered: ‎11-12-2009

ISE isim post-x simulation

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Hi,

 

ISE 13.4 or 14.6 (Only list both as either will do and was wondering if this was depricated in the latest versions?)

VHDL project containg Xilinx IP xores and a ngc file

 

Am I missing something or where in the gui interface do I go to do a post syntheis or post place and route simulation?  With my top-module highlighted I can generate a model for either but on switching to the simulation view and highlighting my testbench the only process on offer is behavioural simulation (which works fine).

 

Where do I look or what do I have to do to get post-syth or post-P&R simulation to be an available option?

 

(For a more global picture, all I want is a vcd (1st choice) or saif file for power estimation)

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Moderator
Moderator
6,076 Views
Registered: ‎06-05-2013

Re: ISE isim post-x simulation

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Hi,

Check the below snapshot

Untitled.png

 

Thanks

 


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Moderator
Moderator
6,077 Views
Registered: ‎06-05-2013

Re: ISE isim post-x simulation

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Hi,

Check the below snapshot

Untitled.png

 

Thanks

 


----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Adventurer
Adventurer
4,593 Views
Registered: ‎11-12-2009

Re: ISE isim post-x simulation

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Thanks!
Don't know how I missed that, too many hours
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Visitor kmkhare
Visitor
4,560 Views
Registered: ‎02-02-2010

Re: ISE isim post-x simulation

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Hello,

When I select Post Map/Post Route simulation option as suggested by you, my test bench vhdl file disappeared and I am able to add it again (it is saying already added in project). and added *_timesim.vhd file Pl.suggest how to proceeed further to do post layout simulation.

Thanks

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