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6,980 Views
Registered: ‎05-04-2012

ISERDES and DDR input

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Hi folks,

I'm just getting my feet wet with implementing an ISERDES with the intent of using it to deserialize DDR data from a source-synchronous ADC. My target device will be an Artix-7.

 

To get familiarized, I setup a simulation where I instantiated an ISERDES2 with DDR and input simulated data from a register. I'm clocking the data out of the register at twice the rate of the clock going into the ISERDES, though the two clocks are phase-aligned. For testing purposes, the clocks are just forced stimulus from the behavioral simulation.

 

Below is my conceptual drawing. Am I missing anything so far?

 

I've read through app notes XAPP524 and XAPP1064, so I realize things may get more complicated when I try to recover the source clock from the output of the ADC as well as the frame clock. 

 

Are these app notes still the best reference for this type of application?

 

Thanks for any advice,

Matthew

 

ISERDES Testbench Implementation concept.png

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Guide avrumw
Guide
12,797 Views
Registered: ‎01-23-2009

Re: ISERDES and DDR input

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Yes, this is better.

 

Note that the DCLK should also come in through an IBUFDS or an IBUF - if it is a source synchronous interface, it would normally also be differential.

 

The DATA_WIDTH would need to be set to 8 and the DATA_RATE to DDR to correspond to the BUFR being in divide by 4 mode.

 

Note that the BUFR can only reach resources in its clock region. If you need the data elsewhere on the die you will need to use a clock crossing FIFO to bring it into a global clock domain.

 

Avrum

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Guide avrumw
Guide
6,968 Views
Registered: ‎01-23-2009

Re: ISERDES and DDR input

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The clocking you are using here is illegal. There is no dedicated connection from a BUFG to a BUFR, and hence there is significant skew between these two. This violates the skew requirement between the CLK and CLKDIV of the ISERDES.

 

The legal clocking schemes of the ISERDES are documented UG471 in the section "ISERDESE2 Clocking Methods".

 

I don't know what you mean by BUFR "8" - are you implying that you are using the divide by 8 of the BUFR? If so, then this too isn't correct. The clock division must correspond to the deserialization. The maximum a single ISERDES can do is 1:8 deserialization (DATA_RATE=8). If the data is coming in DDR, then that means that the maximum division of the BUFR can be 4; 4 cycles of CLK will yield 8 data bits (one on each edge), which will then come out the 8 output pins of the ISERDES on one CLKDIV.

 

Avrum

 

 

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6,960 Views
Registered: ‎05-04-2012

Re: ISERDES and DDR input

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Avrum,

 

Thank you for your reply.

 

I appreciate your pointing out the error in my clock input. Am I correct that a BUFIO would be a better choice? 

 

You are correct in interpretting my illustration. I was suggesting the divide by 8 in the BUFR. Thank you for clarifying how that should work. 

 

Is this illustration more on target?

 

Matthew

 

ISERDES Implementation concept revision 2.png

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Guide avrumw
Guide
12,798 Views
Registered: ‎01-23-2009

Re: ISERDES and DDR input

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Yes, this is better.

 

Note that the DCLK should also come in through an IBUFDS or an IBUF - if it is a source synchronous interface, it would normally also be differential.

 

The DATA_WIDTH would need to be set to 8 and the DATA_RATE to DDR to correspond to the BUFR being in divide by 4 mode.

 

Note that the BUFR can only reach resources in its clock region. If you need the data elsewhere on the die you will need to use a clock crossing FIFO to bring it into a global clock domain.

 

Avrum

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