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Registered: ‎03-01-2016

ISERDESE3 Simulation with FIFO_ENABLE = TRUE -> FIFO_EMPTY = 1

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When using the instantiation below FIFO_EMPTY is never deserted. Is there a parameter/port that needs to change?

 

The goal of the code below is to see the output fifo function.

 

TOOLS:

Vivado 2016.4

 

RTL:

module top(
    input clk,
    input dqs,
    input rst,
    input [7:0] dq
    );

 reg [7:0] iserdes_data;
 wire [7:1] iserdes_data_out;
 wire fifo_empty;

 
 

   ISERDESE3 #(
      .DATA_WIDTH(8),            // Parallel data width (4,8)
      .FIFO_ENABLE("TRUE"),     // Enables the use of the FIFO
      .FIFO_SYNC_MODE("FALSE"),  // Enables the use of internal 2-stage synchronizers on the FIFO
      .IS_CLK_B_INVERTED(1'b1),  // Optional inversion for CLK_B
      .IS_CLK_INVERTED(1'b0),    // Optional inversion for CLK
      .IS_RST_INVERTED(1'b0),    // Optional inversion for RST
      .SIM_DEVICE("ULTRASCALE")  // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
                                 // ULTRASCALE_PLUS_ES2)
   )
   ISERDESE3_inst (
      .FIFO_EMPTY(fifo_empty),           // 1-bit output: FIFO empty flag
      .INTERNAL_DIVCLK(), // 1-bit output: Internally divided down clock used when FIFO is
                                         // disabled (do not connect)

      .Q(iserdes_data_out),                             // 8-bit registered output
      .CLK(dqs),                         // 1-bit input: High-speed clock
      .CLKDIV(),                   // 1-bit input: Divided Clock
      .CLK_B(dqs),                     // 1-bit input: Inversion of High-speed clock CLK
      .D(iserdes_data),                             // 1-bit input: Serial Data Input
      .FIFO_RD_CLK(clk),         // 1-bit input: FIFO read clock
      .FIFO_RD_EN(),           // 1-bit input: Enables reading the FIFO when asserted
      .RST(rst)                          // 1-bit input: Asynchronous Reset
   );
 endmodule   

 

 

Testbench:

`timescale 1ns / 1ps

module sim_top(

    );
    
    real clk_period =(1000000/100)/2; 
    real dqs_period =(1000000/200)/2;
    reg clk, dqs,rst;
    initial begin
      #0 rst = 1'b1;
      #20000 rst = 1'b0;
    end
    always begin
      #0 clk = 1'b0;
      forever #clk_period clk = ~clk;     
    end
    always begin
      #0 dqs = 1'b0;
      forever #dqs_period dqs = ~dqs;     
    end
    top dut(
        .clk(clk),
        .dqs(dqs),
        .rst(rst),
        .dq(8'h27)
        );
    
    
endmodule

current results

Screen Shot 2017-01-23 at 11.46.29 AM.png

 

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Highlighted
4,800 Views
Registered: ‎03-01-2016

CLKDIV is necessary for the module to be used correctly. Referenced in UG974.

 

The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the width of the implemented serialization). It drives the input of the parallel-to-serial converter and the CE module.

 

UG571 only refers to CLKDIV as Low-speed divided clock input, which I mistakenly took as being needed used when FIFO_SYNC_MODE = TRUE.

View solution in original post

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Highlighted
4,801 Views
Registered: ‎03-01-2016

CLKDIV is necessary for the module to be used correctly. Referenced in UG974.

 

The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the width of the implemented serialization). It drives the input of the parallel-to-serial converter and the CE module.

 

UG571 only refers to CLKDIV as Low-speed divided clock input, which I mistakenly took as being needed used when FIFO_SYNC_MODE = TRUE.

View solution in original post

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