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xxst120@123
Visitor
Visitor
2,962 Views
Registered: ‎07-28-2017

ISIM 0X problem

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Ib the following code in ISIM , I have a problem with "Sel" .In Isim, it appears 0x and doesn't work properly. Could you give me a solution,please? ---Thanks

 

 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY prueba2 IS
END prueba2;

ARCHITECTURE behavior OF prueba2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux4a1
PORT(
I1 : IN std_logic_vector(7 downto 0);
I2 : IN std_logic_vector(7 downto 0);
I3 : IN std_logic_vector(7 downto 0);
I4 : IN std_logic_vector(7 downto 0);
E : IN std_logic;
sel : INOUT std_logic_vector(1 downto 0);
F : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal I1 : std_logic_vector(7 downto 0) := (others => '0');
signal I2 : std_logic_vector(7 downto 0) := (others => '0');
signal I3 : std_logic_vector(7 downto 0) := (others => '0');
signal I4 : std_logic_vector(7 downto 0) := (others => '0');
signal E : std_logic := '0';
signal sel : std_logic_vector(1 downto 0) := (others => '0');

--Outputs
signal F : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

-- constant <clock>_period : time := 100 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: mux4a1 PORT MAP (
I1 => I1,
I2 => I2,
I3 => I3,
I4 => I4,
E => E,
sel => sel,
F => F
);

-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--

-- Stimulus process
stim_proc: process
begin
I1 <= "10000001";
I2 <= "10000000";
I3 <= "10000010";
I4 <= "11000001";
Sel <="00";
E <='0';
wait for 500 ns;
end process;

stim_proc1: process
begin
I1 <= "10000001";
I2 <= "10000000";
I3 <= "10000010";
I4 <= "11000001";
Sel <="01";
E <='0';
wait for 500 ns;
end process;

END;

a1.png
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Accepted Solutions
gszakacs
Instructor
Instructor
4,549 Views
Registered: ‎08-14-2007

Even in a test bench it's best to only drive a signal from one process.  If you want to first make the signal low and then later make it high you can simply continue the first process with a state change after the wait statement like:

 

stim_proc: process
begin
I1 <= "10000001";
I2 <= "10000000";
I3 <= "10000010";
I4 <= "11000001";
Sel <="00";
E <='0';
wait for 500 ns;
I1 <= "10000001";
I2 <= "10000000";
I3 <= "10000010";
I4 <= "11000001";
Sel <="01";
E <='0';
wait for 500 ns;
end process;

END;

-- Gabor

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avrumw
Expert
Expert
2,944 Views
Registered: ‎01-23-2009

I am NOT a VHDL expert, but...

 

If I interpret your code properly, the two processes, stim_proc1 and stim_proc2 will start at the same time. The first one drives Sel to 00, and the second one drives it to 01. Together, they resolve to 0x

 

Avrum

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xxst120@123
Visitor
Visitor
2,932 Views
Registered: ‎07-28-2017

Yes , I know 0x assume 00/01 but I want to see them in two separate time frames. But they mix themselves inA one, showing me "0x".Is there any way to see them in two parts? 

PS: Do I have to check the clock or something like that ? 

Thanks for answering . 

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gszakacs
Instructor
Instructor
4,550 Views
Registered: ‎08-14-2007

Even in a test bench it's best to only drive a signal from one process.  If you want to first make the signal low and then later make it high you can simply continue the first process with a state change after the wait statement like:

 

stim_proc: process
begin
I1 <= "10000001";
I2 <= "10000000";
I3 <= "10000010";
I4 <= "11000001";
Sel <="00";
E <='0';
wait for 500 ns;
I1 <= "10000001";
I2 <= "10000000";
I3 <= "10000010";
I4 <= "11000001";
Sel <="01";
E <='0';
wait for 500 ns;
end process;

END;

-- Gabor

View solution in original post

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xxst120@123
Visitor
Visitor
2,820 Views
Registered: ‎07-28-2017

Thank you ,sir.

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