09-18-2018 07:52 AM - edited 09-18-2018 07:54 AM
This issue has been raised before, but not I think for user RTL code, only CoreGen.
I have a design that is working on the bench and actually previously simulated. I need to make a variant of the code so created a new project from scratch. It synthesizes but I cannot simulate it because I get this warning:
[VRFC 10-122] xtx800_toplevel remains a black-box since it has no binding entity ["C:/Xilinx_Projects/XTX800_VC707_SCCC_IF/XTX800_VC707_SCCC_IF.srcs/sim_1/new/XTX800_TOPLEVEL_TB.vhd":274]
ISIM opens but the instantiated component "TOPLEVEL" has not been compiled. In the Simulation Sources window there is a red question mark next to toplevel.vhd. I cannot figure out the reason for this. I copied the source and simulation files to Microsemi Modelsim (its free) and that runs through no problem (see attached).
I deleted toplevel.vhd from the project, re-added it, checked it was set to synthesis and simulation, but still red question mark. I believe the syntax is good or Modelsim would have complained. Nevertheless, as a check I then made a simple RTL file called test.vhd. Again I have the same problem. Both files are in library xil_defaultlib.
Excerpts from my test bench:
Port ( TEST_I : in STD_LOGIC;
TEST_O : out STD_LOGIC);
U00: test port map ( TEST_I => '0', TEST_O => open);
Anyone seen this before please?
09-18-2018 08:01 AM
09-18-2018 08:35 AM
Thanks for the reply. I did actually see this prior to raising this post. Hierarchy update defaults to "automatic update and compile order" already so no luck there I'm afraid.
09-18-2018 11:46 PM - edited 09-18-2018 11:47 PM
Can you please share a test case with us to investigate this issue at our end. Also, can you please let us know which version of Vivado are you using and please share the vivado.log file.
Thanks & Regards,