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subashrajam
Contributor
Contributor
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Registered: ‎10-03-2016

ISIM - mixed language simulation - FDCE primitive error

 I am adding the Verilog module instantiation in VHDL testbench. In my Verilog file, there is FDCE primitive. While running Fuse command. it shows the error in the attached file.

 

Q1) How to include the primitive libraries in fuse command?

temp1.jpg
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bandi
Moderator
Moderator
607 Views
Registered: ‎09-15-2016

Hi @subashrajam,

 

You can include the libraries to the fuse command as follows:

 

fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o C:/Users/bandi/simulation_dev/ise_model_pe/tb_fdce_isim_beh.exe -prj C:/Users/bandi/simulation_dev/ise_model_pe/tb_fdce_beh.prj work.tb_fdce work.glbl {}

 

For more information on options to fuse command please refer the below link:

 

https://www.xilinx.com/itp/xilinx10/isehelp/ism_cl_fuse_options.html

 

If you are still facing the issue then can you please share the fuse.log and the test case to reproduce and check this issue at our end.

 

Thanks & Regards,

Sravanthi B

 

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Thanks & Regards,
Sravanthi B
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