cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
811 Views
Registered: ‎10-16-2018

ISIM simulation clock problem

Jump to solution

In ISIM simulation, why does the clock signal stay low for so long and how to make it return to normal state?

微信图片_20190426154335.png
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
529 Views
Registered: ‎05-31-2017

Re: ISIM simulation clock problem

Jump to solution

Hi @nia_z ,

I did give a quick try with the shared steps to reproduce and in the above posts, you have mentioned that this clock is a test bench clock. But checking the source code of the top.v file it seems that the clock which you have mentioned is not a test bench clock but the clock generated from the PLL as shown in the below snippet of the code obtained from top.v file 

code.JPG

Below is the waveform 

clk_wave_new.JPG

View solution in original post

0 Kudos
14 Replies
Highlighted
Xilinx Employee
Xilinx Employee
784 Views
Registered: ‎07-16-2008

回复: ISIM simulation clock problem

Jump to solution

How did you specify clock stimulus in test bench?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
779 Views
Registered: ‎10-16-2018

回复: ISIM simulation clock problem

Jump to solution
 
微信图片_20190428091234.png
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
774 Views
Registered: ‎07-16-2008

回复: ISIM simulation clock problem

Jump to solution

I don't see anything out of order from the snapshot. Any other factors that may influence the clock toggling?

Can you please share a test case for a look?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
751 Views
Registered: ‎06-21-2017

Re: ISIM simulation clock problem

Jump to solution

Is the clock shown the test bench clock or the output of a DCM?  The DCM will require some time to lock.

Highlighted
Visitor
Visitor
736 Views
Registered: ‎10-16-2018

回复: ISIM simulation clock problem

Jump to solution
 
0 Kudos
Highlighted
Visitor
Visitor
732 Views
Registered: ‎10-16-2018

Re: ISIM simulation clock problem

Jump to solution
the test bench clock
0 Kudos
Highlighted
Moderator
Moderator
729 Views
Registered: ‎09-15-2016

Re: ISIM simulation clock problem

Jump to solution

Hi @nia_z ,

Can you please share the complete test case or the archived project to check this issue at our end? 

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
722 Views
Registered: ‎10-16-2018

Re: ISIM simulation clock problem

Jump to solution
 
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
699 Views
Registered: ‎07-16-2008

Re: ISIM simulation clock problem

Jump to solution

The test bench alone cannot be used to reproduce the problem. Please share the entire design so that we can perform the simulation locally and see what the result is.

 

BTW, in the wave snapshot, is the 'clk' added from the top level or submodule? Is it a behavioral simulation?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
660 Views
Registered: ‎10-16-2018

Re: ISIM simulation clock problem

Jump to solution

The clock signal defined in the simulation module.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
652 Views
Registered: ‎07-16-2008

Re: ISIM simulation clock problem

Jump to solution

I do not observe the same result as what you posted. I just performed top level behavioral simulation and ran the default 1000ns. The 'clk' signal toggles as expected.

wave.JPG

 

Please describe in detail the steps to reproduct the issue.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
640 Views
Registered: ‎10-16-2018

Re: ISIM simulation clock problem

Jump to solution
 
0 Kudos
Highlighted
Moderator
Moderator
530 Views
Registered: ‎05-31-2017

Re: ISIM simulation clock problem

Jump to solution

Hi @nia_z ,

I did give a quick try with the shared steps to reproduce and in the above posts, you have mentioned that this clock is a test bench clock. But checking the source code of the top.v file it seems that the clock which you have mentioned is not a test bench clock but the clock generated from the PLL as shown in the below snippet of the code obtained from top.v file 

code.JPG

Below is the waveform 

clk_wave_new.JPG

View solution in original post

0 Kudos
Highlighted
Visitor
Visitor
506 Views
Registered: ‎10-16-2018

Re: ISIM simulation clock problem

Jump to solution

Yes, you are right. And the problem has been solved.

0 Kudos