10-14-2009 12:06 PM - edited 10-14-2009 12:07 PM
I get the following error while trying to do a Post Route simulation:
ERROR:HDLCompiler:104 - "/home/crazor/git/spi/sim/work/../../src/tb_spi.vhd" Line 6: Cannot find <spi_pkg> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
The exact same code passes behavioural simulation and synthesizes fine. I'm using 11.3.
package spi_pkg is
10-15-2009 11:33 AM
From the cut and paste it is not clear which file has the package. If the actual package is part of the testbench, then you may want to check your library use statement to see if it is expecting a library called spi_pkg. If it is a seperate file, then please ensure this gets compiled as well. If it passes behavioral simulation, then that means this file is being compiled as part of your source files, although when you run post-route simulation, it is no longer seen since the only file you would see is output from Netgen, the SDF file and the testbench., You may want to see where this package file is siting and if it can be seen when you change to the post-route simulation. This will give you clues as to what may be going on here.
10-15-2009 11:47 AM
there's the file spi_pkg.vhd which defines the package spi_pkg, as copied above (note the package statement). It contains record types and a component. Then there is the file spi.vhd which implements the actual logic and the testbench tb_spi.vhd. Both spi.vhd and tb_spi.vhd have the use statement to make the package's contents visible.
I too assume that the spi_pkg.vhd does not get compiled. How would I go about adding that file to the post-route sim so it gets compiled as well?
10-16-2009 09:01 AM
As far as I know there is no mechanism to handle this directly in PN. Although there is a way to work around this. What you can do is to create a custom project file that includes your spi_pkg.vhd and then this will work correctly. Here are some steps to make this happen:
1. Edit the <testbench>_par.prj file that can be found in your project directory
2. Add in the file that you want. I suspect it would be the following:
vhdl spi_pkg spi_pkg.vhd
3. Save this file with a new name, although use the same extension
These next steps can be seen in the Project Navigator Help as well
4. Then right click on the "Simulate Post-Place & Route Model" and select properties
5. Select the option that says use custom project file and then below it you can point to the file
6. Point to the newly created project file and hit OK
Now each time you run your timing simulation, you will have this file get compiled correctly.
Hope this helps.
02-07-2011 08:38 AM
Glad I found this through Google. This does help - thanks!
However, it's quite irritating to have to do this to run a post-routing simulation. We have a global defs.vhd file (with the proper package declarations, etc.) that is included in a lot of things, including the testbench top-level. What's puzzling is that the BFM files (both package and entity) get compiled just fine in the post-route sim, but the defs file does not. I can't quite spot a correlation, except that the defs file does not contain definitions for anything other than a lot of constants (i.e. no instantiated entities or types like the BFM package files).
Is there any chance of a resolution on this soon? Should I file this as a problem report?
05-31-2012 07:15 AM
I am also facing the same problem "Cannot find <xxxxx> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file." in post route simulation. I tried all the solutions from Xilinx forums, please tell me what is the solution for it.
06-15-2012 04:10 AM
12-27-2012 03:21 AM
Is it correct to say this is a known problem with the Xilinx ISE tools, and that instead of fixing the problem, Xilinx is asking customers to manually work around the problem?
04-05-2018 03:53 PM
I also encountered this problem when I tried to use a package to pass the internal signal to test bench. I've tried the custom project file and it worked. However, although the package was successfully compiled, the signal is not passing from the my design to test bench.
the way I tried to use the package is:
first I generated a package
use IEEE.STD_LOGIC_1164.all; package tracepkg is -- synthesis translate_off signal check_point: std_logic_vector (7 downto 0); -- synthesis translate_on end tracepkg;
and I referenced the package and assigned to the global signal in my design:
use work.tracepkg.ALL; entity my_design is .... -- synthesis translate_off check_point <= u; -- synthesis translate_on
then referenced the package and read the signal in test bench:
Use work.tracepkg.ALL; entity tb is .... signal test : std_logic_vector(7 downto 0) := (others => '0'); ..... test<= check_point;
in the behavior model the value pass to the test signal, but in timing simulation it doesn't :(