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Visitor kpatel94126
Visitor
10,410 Views
Registered: ‎02-22-2015

ISim Simulator error

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I get the following errors when running a simulation Behaviour Check on ISI 14.7

 

Line 26: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="

Line 8: unit ,bench. ignored due to previous errors.

 

 

Please help. How do i fix?

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Xilinx Employee
Xilinx Employee
18,035 Views
Registered: ‎04-16-2012

Re: ISim Simulator error

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Hello @kpatel94126 

 

The issue here is "used ,(comma) instead of ;(semicolon)"

I ran simulation succesfully after modifying the below lines in MUX4_TB.vhd:

 

TSEL <= "00",
TA <= '0';

 

to

 

TSEL <= "00";

TA <= '0';

 

Thanks,

Vinay

 

 

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8 Replies
Xilinx Employee
Xilinx Employee
10,400 Views
Registered: ‎02-16-2014

Re: ISim Simulator error

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hi,

 

There are some syntax errors in your code.

 

--------- 4-to-1-Multiplexor ------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX4 is
  port (SEL		: in STD_LOGIC_VECTOR(1 downto 0);
	A, B, C, D	: in STD_LOGIC;
	F		: out STD_LOGIC);
end MUX4;

architecture BEHAVIOUR of MUX4 is
  signal SEL1, SEL1B, SEL0, SEL0B: STD_LOGIC;
begin
  SEL1	<= SEL(1);
  SEL1B <= not SEL(1);
  SEL0	<= SEL(0);
  SEL0B	<= not SEL(0);

  F <= 	(A and SEL1B and SEL0B) or
	(B and SEL1B and SEL0 ) or
	(C and SEL1 and SEL0B ) or
	(D and SEL1 and SEL0 );
end;



--------- Testbench ------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX4_TB is
end MUX4_TB;

architecture BENCH of MUX4_TB is

  signal TSEL: STD_LOGIC_VECTOR(1 downto 0);
  signal TA, TB, TC, TD, TF: STD_LOGIC;

begin

M: entity work.MUX4(BEHAVIOUR) port map (
  A	=> TA,
  B	=> TB,
  C	=> TC,
  D	=> TD,
  SEL	=> TSEL,
  F	=> TF
);

process
begin
  TSEL	<= "00";
  TA	<= '0';
  TB	<= '0';
  TC	<= '0';
  TD	<= '0';
wait for 10 NS;
  TA	<= '1';
wait for 10 NS;
  TA	<= '0';
wait for 10 NS;

  TSEL	<= "01";
wait for 10 NS;
  TB	<= '1';
wait for 10 NS;
  TB	<= '0';
wait for 10 NS;

  TSEL	<= "10";
wait for 10 NS;
  TC	<= '1';
wait for 10 NS;
  TC	<= '0';
wait for 10 NS;

  TSEL	<= "11";
wait for 10 NS;
  TD	<= '1';
wait for 10 NS;
  TD	<= '0';
wait for 10 NS;

  wait;
end process;

end BENCH;

 I corrected them and able to run the simulation.

 

These are the modifications that I have done.

  1. There should be ; in this line after all in line4.
  2. The values that are assigned to TSEL should be used with "" as it is a std_logic_vector.
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Xilinx Employee
Xilinx Employee
10,399 Views
Registered: ‎02-14-2014

Re: ISim Simulator error

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Hello,

I am able to launch the ISIM simulator with your design just after removing syntax errors. I am using ISE 14.7.

Regards,
Ashish
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Visitor kpatel94126
Visitor
10,379 Views
Registered: ‎02-22-2015

Re: ISim Simulator error

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Thanks for your reply. I have corrected these errors (which were introduced in the txt file i editted for this post, not in my original VHDL code)

 

The 2 errors still exist when i try to simulate.

 

Is there any process required before I run "Behavioural Check Syntax" in ISE Simulator? I am very new to VHDL

 

I have compiled my VHDL by right clicking "Generate Programming File" in implementation window and selecting "Rerun All". All showing green.

Then i have proceeded to Simulation window and run "Behavioural Check Syntax" - Fails with 2 aforementioned failures

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Xilinx Employee
Xilinx Employee
10,371 Views
Registered: ‎02-14-2014

Re: ISim Simulator error

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Hello,

 

Testbenches are used for simulation purpose so you need to have two different .vhd files in your project and change the association of testbench to simulation while adding it to project.so tool won't show any error in synthesis. I am able to launch simulator successfully this way as well.

 

Check the attached image and Change the association field to simulation as seen in the snapshot.

 

If you still face any issue, is it possible to attach complete project? Are there any other files also in your design?

 

Regards,
Ashish
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Visitor kpatel94126
Visitor
10,360 Views
Registered: ‎02-22-2015

Re: ISim Simulator error

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When i right click on the tench bench .vhd and select "source properties", the view association fieldis set to "simulation" so i think this is all correct. I will try to attach the project later today. Unfortunately my project laptop is not networked. Thanks for your comment.
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Visitor kpatel94126
Visitor
10,346 Views
Registered: ‎02-22-2015

Re: ISim Simulator error

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Project attached.

Appreciate any help.

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Xilinx Employee
Xilinx Employee
18,036 Views
Registered: ‎04-16-2012

Re: ISim Simulator error

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Hello @kpatel94126 

 

The issue here is "used ,(comma) instead of ;(semicolon)"

I ran simulation succesfully after modifying the below lines in MUX4_TB.vhd:

 

TSEL <= "00",
TA <= '0';

 

to

 

TSEL <= "00";

TA <= '0';

 

Thanks,

Vinay

 

 

--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.

View solution in original post

Visitor kpatel94126
Visitor
10,327 Views
Registered: ‎02-22-2015

Re: ISim Simulator error

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Excellent works now !!!

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