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8,777 Views
Registered: ‎01-08-2015

ISim doesn't work propery when parallel block (fork) is disabled.

Hello, I'm using ISim 14.6(nt64)  P.68d.

This ISim will not work propery when parallel block is disabled.

 

The fllowing test rtl shows a example.

 

[ test rtl ]

module TEST_ISIM;
reg    a;

 

initial begin
    a = 0;
    #10;
    fork
        begin : seq_block0
            #10;
            $display("end of seq_block0");
            disable seq_block1;
        end
        begin : seq_block1
            wait(a);
            $display("end of seq_block1"); // this display will never execute?
        end
    join
    $display("end of parallel_block");
    #10;
    a = 1'b1; // reg a raised here,but seq_block1 is already killed.
    #10;
    $display("finish");
    $finish;
end

endmodule

 

[ ISim simulation result ]

end of seq_block0

end of parallel_block

end of seq_block1

finish

 

[ Simulatioin result with other simulators ]

end of seq_block0

end of parallel_block

finish

 

 

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5 Replies
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Xilinx Employee
Xilinx Employee
8,768 Views
Registered: ‎04-16-2012

Hello,

Check this answer record: http://www.xilinx.com/support/answers/36304.html

Thanks,
Vinay
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Xilinx Employee
Xilinx Employee
8,764 Views
Registered: ‎02-14-2014

Hello,

The issue was under investigation and CR was already filed to take care of this problem. This issue seems to be fixed in Vivado Simulator. You can check with latest Vivado version or proceed with the workaround mentioned in answer record pointed by Vinay.
Regards,
Ashish
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Moderator
Moderator
8,754 Views
Registered: ‎07-21-2014

Hi,

 

This design is working as expected in Vivado 2014.4 XSIM.

Use updated tools for better results.

 

XSIM output:

end of seq_block0
end of parallel_block
finish
$finish called at time : 40 ns

 

Thanks,
Anusheel
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Highlighted
8,741 Views
Registered: ‎01-08-2015

Thank you for your responce.

 

I've understand the current status, and I'll try Vivado vesion.

 

 

By the way, I can find same defect with while statement in fork block.

 

[ sample ]

module TEST_ISIM;

reg    a;

initial begin
    a = 0;
    #10;
    fork
        begin : seq_block0
            #10;
            $display("end of seq_block0");
            disable seq_block1;
        end
        begin : seq_block1
            while(~a) #1; // wait statement is changed to while statement
            $display("end of seq_block1"); // this display will never execute?
        end
    join
    $display("end of parallel_block");
    #10;
    a = 1'b1; // reg a raised here,but seq_block1 is already killed.
    #10;
    $display("finish");
    $finish;
end

endmodule

 

[ ISim simulation result ]

end of seq_block0

end of parallel_block

end of seq_block1

finish

 

[ another simulator result ]

end of seq_block0

end of parallel_block

finish

 

 

not only wait, but also while statement is not supported in fork block ?

 

 

Regards.

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Xilinx Employee
Xilinx Employee
8,701 Views
Registered: ‎02-14-2014

Hello,

I checked this with Vivado Simulator (Design Suite 2014.4) and below is the output with while statement

end of seq_block0
end of parallel_block
finish
$finish called at time : 40 ns
Regards,
Ashish
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