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ledoute
Visitor
Visitor
11,580 Views
Registered: ‎02-17-2011

ISim under Ubuntu 11.04

Hey guys,

I'm running into a problem when trying to use ISim under Ubuntu 64bit.

 

This is my logfile:

 

Started : "Simulate Behavioral Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib secureip -o /home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/TB_USER_MEMORY_isim_beh.exe -prj /home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/TB_USER_MEMORY_beh.prj work.TB_USER_MEMORY {-mt off -v 1}
Running: /opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/TB_USER_MEMORY_isim_beh.exe -prj /home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/TB_USER_MEMORY_beh.prj work.TB_USER_MEMORY -mt off -v 1
ISim O.40d (signature 0xdc0cde0)
Turned off multi-threading for compilation
Determining compilation order of HDL files
The vhdl library search path for library \"std\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/std\"
The veri library search path for library \"std\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/std\"
The vhdl library search path for library \"ieee\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/ieee\"
The veri library search path for library \"ieee\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/ieee\"
The vhdl library search path for library \"ieee_proposed\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/ieee_proposed\"
The veri library search path for library \"ieee_proposed\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/ieee_proposed\"
The vhdl library search path for library \"vl\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/vl\"
The veri library search path for library \"vl\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/vl\"
The vhdl library search path for library \"synopsys\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/synopsys\"
The veri library search path for library \"synopsys\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/synopsys\"
The vhdl library search path for library \"simprim\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/simprim\"
The veri library search path for library \"simprim\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/simprim\"
The vhdl library search path for library \"unisim\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/unisim\"
The veri library search path for library \"unisim\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/unisim\"
The vhdl library search path for library \"unimacro\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/unimacro\"
The veri library search path for library \"unimacro\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/unimacro\"
The vhdl library search path for library \"aim\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/aim\"
The veri library search path for library \"aim\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/aim\"
The vhdl library search path for library \"cpld\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/cpld\"
The veri library search path for library \"cpld\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/cpld\"
The vhdl library search path for library \"pls\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/pls\"
The veri library search path for library \"pls\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/pls\"
The vhdl library search path for library \"xilinxcorelib\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/xilinxcorelib\"
The veri library search path for library \"xilinxcorelib\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/vhdl/hdp/lin64/xilinxcorelib\"
The vhdl library search path for library \"aim_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/aim_ver\"
The veri library search path for library \"aim_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/aim_ver\"
The vhdl library search path for library \"cpld_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/cpld_ver\"
The veri library search path for library \"cpld_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/cpld_ver\"
The vhdl library search path for library \"simprims_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/simprims_ver\"
The veri library search path for library \"simprims_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/simprims_ver\"
The vhdl library search path for library \"unisims_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/unisims_ver\"
The veri library search path for library \"unisims_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/unisims_ver\"
The vhdl library search path for library \"uni9000_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/uni9000_ver\"
The veri library search path for library \"uni9000_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/uni9000_ver\"
The vhdl library search path for library \"unimacro_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/unimacro_ver\"
The veri library search path for library \"unimacro_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/unimacro_ver\"
The vhdl library search path for library \"xilinxcorelib_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/xilinxcorelib_ver\"
The veri library search path for library \"xilinxcorelib_ver\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/xilinxcorelib_ver\"
The vhdl library search path for library \"secureip\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/xip/secureip\"
The veri library search path for library \"secureip\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/xip/secureip\"
The vhdl library search path for library \"work\" is now \"/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/isim/work\"
The veri library search path for library \"work\" is now \"/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/isim/work\"
The vhdl library search path for library \"secureip\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/xip/secureip\"
The veri library search path for library \"secureip\" is now \"/opt/Xilinx/13.1/ISE_DS/ISE/verilog/hdp/lin64/xip/secureip\"

-- Dumping Relevant Parameters
XILINX = /opt/Xilinx/13.1/ISE_DS/ISE/
PATH = /opt/Xilinx/13.1/ISE_DS/ISE//bin/lin64:/opt/Xilinx/13.1/ISE_DS/common/bin/lin64:/opt/Xilinx/13.1/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/13.1/ISE_DS/PlanAhead/bin:/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64:/opt/Xilinx/13.1/ISE_DS/ISE/sysgen/util:/opt/Xilinx/13.1/ISE_DS/EDK/bin/lin64:/opt/Xilinx/13.1/ISE_DS/EDK/gnu/microblaze/lin64/bin:/opt/Xilinx/13.1/ISE_DS/EDK/gnu/powerpc-eabi/lin64/bin:/opt/Xilinx/13.1/ISE_DS/common/bin/lin:/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin:/opt/Xilinx/13.1/ISE_DS/EDK/bin/lin:/o
pt/Xilinx/13.1/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/13.1/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games
LD_LIBRARY_PATH = /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64:/opt/Xilinx/13.1/ISE_DS/common/lib/lin64:/opt/Xilinx/13.1/ISE_DS/ISE/sysgen/lib:/opt/Xilinx/13.1/ISE_DS/ISE/lib/lin64:/opt/Xilinx/13.1/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/opt/Xilinx/13.1/ISE_DS/EDK/lib/lin64:/opt/Xilinx/13.1/ISE_DS/common/lib/lin:/opt/Xilinx/13.1/ISE_DS/ISE/lib/lin:/opt/Xilinx/13.1/ISE_DS/ISE/smartmodel/lin/installed_lin/lib:/opt/Xilinx/13.1/ISE_DS/EDK/lib/lin
PWD = /home/henry
CWD = /home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70
GCC = /usr/bin/gcc
-- Done dumping Relevant Parameters

-- Dumping System Information
sysname = Linux
release = 2.6.38-5-generic
version = #32-Ubuntu SMP Tue Feb 22 16:10:15 UTC 2011
machine = x86_64
ram = 6117532 KB
-- Done dumping System Information

-- Dumping Loaded Modules

/lib/x86_64-linux-gnu/libc.so.6
/lib/x86_64-linux-gnu/libdl.so.2
/lib/x86_64-linux-gnu/libgcc_s.so.1
/lib/x86_64-linux-gnu/libm.so.6
/lib/x86_64-linux-gnu/libpthread.so.0
/lib/x86_64-linux-gnu/libuuid.so.1
/lib64/ld-linux-x86-64.so.2
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libCit_Core.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libICR.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libMiniZip.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libPersonalityModule.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libPort_Std.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libPortability.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libPrjrep_Clientac.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libStaticFileParsers.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libThread.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libUtilities.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libVrfc_Verific.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libVrfc_Vhdl_Sort.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libZlib.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_bzip2-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_date_time-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_filesystem-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_iostreams-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_program_options-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_regex-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_system-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_thread-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libboost_zlib-gcc41-mt-p-1_38.so.1.38.0
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libisl_iostreams.so
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstlport.so.5.1
/opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libxercesc.so
/opt/Xilinx/13.1/ISE_DS/ISE/lib/lin64/libUtilC_MessageDispatcher.so
-- Done dumping Loaded Modules

-- Dumping library mapping
aim=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/aim
aim_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/aim_ver
cpld=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/cpld
cpld_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/cpld_ver
ieee=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/ieee
ieee_proposed=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/ieee_proposed
pls=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/pls
secureip=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/xip/secureip
simprim=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/simprim
simprims_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/simprims_ver
std=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/std
synopsys=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/synopsys
uni9000_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/uni9000_ver
unimacro=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/unimacro
unimacro_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/unimacro_ver
unisim=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/unisim
unisims_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/unisims_ver
vl=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/vl
work=isim/work
xilinxcorelib=/opt/Xilinx/13.1/ISE_DS/ISE/./vhdl/hdp/lin64/xilinxcorelib
xilinxcorelib_ver=/opt/Xilinx/13.1/ISE_DS/ISE/./verilog/hdp/lin64/xilinxcorelib_ver
-- Done dumping library mapping

Parsing VHDL file "/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/RTL/Henrys_Sources/USER_DESIGN.vhd" into library work
Parsing entity <USER_DESIGN>.
Parsing architecture <ADDER> of entity <user_design>.
INFO:HDLCompiler:1692 - "/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/RTL/Henrys_Sources/USER_DESIGN.vhd" Line 87. Clock event situations found in this design unit may cause RTL and post-synthesis simulation mismatch in specific cases. Use of the standardized rising_edge and falling_edge functions is recommended instead.
INFO:HDLCompiler:1692 - "/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/RTL/Henrys_Sources/USER_DESIGN.vhd" Line 97. Clock event situations found in this design unit may cause RTL and post-synthesis simulation mismatch in specific cases. Use of the standardized rising_edge and falling_edge functions is recommended instead.
Parsing VHDL file "/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/RTL/Henrys_Sources/fifo_256x32.vhd" into library work
Parsing entity <fifo_256x32>.
Parsing architecture <fifo_256x32_a> of entity <fifo_256x32>.
Parsing VHDL file "/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/RTL/Henrys_Sources/USER_MEMORY.vhd" into library work
Parsing entity <USER_MEMORY>.
Parsing architecture <STORAGE> of entity <user_memory>.
Parsing VHDL file "/home/henry/h264_Xilinx_Projekt/PCIE_DMA_h264_V5FX70/RTL/Henrys_Sources/TB_USER_MEMORY.vhd" into library work
Parsing entity <TB_USER_MEMORY>.
Parsing architecture <behavior> of entity <tb_user_memory>.
Starting static elaboration
Executing TB_USER_MEMORY(behavior)
WARNING:HDLCompiler:746 - "/build/xfndry10/O.40d/rtf/vhdl/src/ieee/numeric_std.vhd" Line 878: Range is empty (null range)
WARNING:HDLCompiler:746 - "/build/xfndry10/O.40d/rtf/vhdl/src/ieee/numeric_std.vhd" Line 879: Range is empty (null range)
Executing USER_MEMORY_default(STORAGE)
Executing fifo_256x32_default(fifo_256x32_a)
Executing \fifo_generator_v6_2(1,0,9,"BlankString",32,"0",32,0,"virtex5",0,0,0,0,1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,"BlankString",0,0,0,1,"512x36",4,5,0,255,254,0,9,256,1,8,0,1,0,0,0,1,0,0,9,256,1,8,1,1,1,0)(1,11,1,1,1,7,1,11,1,6)\(behavioral)
Executing \fifo_generator_v6_2_bhv_ss(9,32,"0",32,0,0,0,1,0,1,0,0,0,0,1,0,0,1,4,5,0,255,254,0,256,8,0,1,0,0,0,0,256,8,100,1,0)(1,1)\(behavioral)
Executing \fifo_generator_v6_2_bhv_preload0("0",32,1,0,1,0,0,0,100,1,0,1)(1,1)\(behavioral)
Executing USER_DESIGN_default(ADDER)
Completed static elaboration
Fuse Memory Usage: 88320 KB
Fuse CPU Usage: 240 ms
Using precompiled package standard from library std
Using precompiled package std_logic_1164 from library ieee
ICR Memory Use: 4294967295 bytes
Using precompiled package numeric_std from library ieee
ICR Memory Use: 4294967295 bytes
Using precompiled package std_logic_arith from library ieee
ICR Memory Use: 4294967295 bytes
Using precompiled package std_logic_unsigned from library ieee
ICR Memory Use: 4294967295 bytes
Compiling package vcomponents - p_0947159679
ICR Memory Use: 4294967295 bytes
Compiling isim/TB_USER_MEMORY_isim_beh.exe.sim/unisim/p_0947159679.c to isim/TB_USER_MEMORY_isim_beh.exe.sim/unisim/p_0947159679.lin64.o with command:
"/usr/bin/gcc" -Wa,-W  -O  -fPIC  -m64  -c -o "isim/TB_USER_MEMORY_isim_beh.exe.sim/unisim/p_0947159679.lin64.o" -I"/opt/Xilinx/13.1/ISE_DS/ISE/./data/include" "isim/TB_USER_MEMORY_isim_beh.exe.sim/unisim/p_0947159679.c"
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.14' not found (required by /usr/lib/libppl_c.so.2)
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl_c.so.2)
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl_c.so.2)
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.14' not found (required by /usr/lib/libppl.so.7)
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl.so.7)
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl.so.7)
/usr/lib/x86_64-linux-gnu/gcc/x86_64-linux-gnu/4.5.2/cc1: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libgmpxx.so.4)
FATAL_ERROR:Simulator:Fuse.cpp:500:1.128.12.1 - Failed to compile generated C file isim/TB_USER_MEMORY_isim_beh.exe.sim/unisim/p_0947159679.c

     Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
FATAL_ERROR:Simulator:Fuse.cpp:500:1.128.12.1 - Failed to compile generated C file isim/TB_USER_MEMORY_isim_beh.exe.sim/unisim/p_0947159679.c

     Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Simulate Behavioral Model" failed

 

 

Is this a known issue? Any idea how to solve this?

Best regards

 

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8 Replies
leonmeier
Newbie
Newbie
11,559 Views
Registered: ‎04-12-2011

Hello

 

try gcc-4.4:

 

sudo rm /usr/bin/gcc

sudo ln -s /usr/bin/gcc-4.4 /usr/bin/gcc

ledoute
Visitor
Visitor
11,520 Views
Registered: ‎02-17-2011

Thx mate,

changed the gcc to 4.4, now it works.

Maybe this should be in some xilinx answer record???

I mean Ubuntu isn't officially supported, but this little workaround

might help some people...

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mentor
Newbie
Newbie
10,958 Views
Registered: ‎07-02-2011

Thank leonmeier. I worked on this solution, ISE WebPack 13.1  kubuntu 11.4

 

 

0 Kudos
9,620 Views
Registered: ‎05-10-2012

I changed the symlink to gcc-4.4. Didn't work for me on Ubuntu 11.04 64 bit, ISE is 13.3.

 

I hope someone finds a solution. I'll try it on a windows vm in the meanwhile.

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eternialogic
Visitor
Visitor
7,218 Views
Registered: ‎02-01-2014

just tested it on Kubuntu::

 

You have to use Gcc-4.4, not 4.7 it only likes 4.4 for some reason.

debrajr
Moderator
Moderator
7,213 Views
Registered: ‎04-17-2011

Thats a good workaround. Thanks for posting. But do note that Ubuntu is not a supported OS for running Xilinx tools.
Regards,
Debraj
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eternialogic
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5,774 Views
Registered: ‎02-01-2014

Welp, xilinx works perfectly in ubuntu so...
Good job!
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vijayak
Xilinx Employee
Xilinx Employee
5,705 Views
Registered: ‎10-24-2013

Hi,
Please mark the solution in the interest of other users.
Thanks,Vijay
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