Implementation passes. Elab fails for Post impleentation simulation saying port not found.

[bhawandeepsingh]

HI all,

I have an IP. I am facing a strange error

The implementation passess. But when I try to run post implementation simulation, it gives the below message(s) for a subIP instantiated in the design.

ERROR: [VRFC 10-426] cannot find port ena on this module [/home/saiuser/Documents/BhawandeepSIngh/XilinxVivado/VivadoProjs/shared_prach_verification/feb4/uplink/uplink.srcs/sources_1/imports/Source/wrapper/cv_len_lut_r8_d16_wrapper_prach.v:35]

I checked the file mentioned on line number mentioned - it is a module instantiation. I checked that instantiated module's definition and it has ena port.

It is just the first error -there are others after this - but I think they are due to this error only.

Anyone has any idea why this could be happening ?

Thanks a lot in advance and sincerely

Bhawandeep SIngh

[shameera]

Hi @bhawandeepsingh,

I hope that you are facing issues in post-implementation functional simulation. Did you try running post-synthesis functional simulation ? Was it working fine ?

There might be a chance of Vivado tool trimming the port. So, can you once check in the synthesis and implementation log to see if you find any info/warning regarding trimming of the port.