04-29-2019 03:07 AM
I have a 16 bit bus in the design, but in the Synthesized design all signals of the bus appear as separate signals. But anyway, they are different signals from [0:0] to [15:15], every one of them on a different probe input of the ila core. So in the Waveform window, I opened the Add probes window, selected the 16 signals, and added them to the waveform.
Unfortunately all the added signals became [0:0].
04-29-2019 04:56 AM
First, to see if this is a naming issue or a connection issue, do you see those signals connected to ILA probes as expected in the Implemented design? You can check this by Schematic.
04-29-2019 05:17 AM
Yes, I can see the signals connected to the ILA core. On the left you can see the i_system block, on the right the u_ila_0 block.
04-29-2019 06:57 AM
From what I see of your screen capture, your 16-bit bus has been split out into 16 individual nets. I would suggest a couple of options:
1) In the waveform viewer you can define a "virtual bus" and add each of the 16 probes to it,
2) In your BD, use a "concat" block to bundle the 16 nets back into a a 16-bit bus, then connect the bus to one port of the ILA.
04-29-2019 07:12 AM
OK, thank you. But I still have questions.
1. I defined a Virtual bus, but how can I add a probe to it? Yes, I can add a [0:0] to it, simple move the signal on the virtual bus. But I cannot add [1:1], because the main problem is, that I cannot add [1:1] to the waveform.
2. In BD (Block Design) these are already a bus. Only in the Synthesis Design has it been split to individual nets.
04-29-2019 07:29 AM
Can you try "write_debug_probes" command to generate the ltx file in the implemented design?
And use this new generated ltx file to replace the original one that was generated along with the bit file.
04-29-2019 07:45 AM
I regenerated the ltx file from command line. It is practically the same. But as I read it, I wonder, if I can edit it manually. I can see what is the difference between a single net and a bus.
06-11-2019 05:48 AM
Has anyone found a solution to this problem? I have the same malfunction (since Vivado version 2018.3). I had hoped it would be fixed with Vivado 2019.1, but unfortunately I still get this bug.
06-11-2019 11:29 PM
06-12-2019 04:35 AM
What should I change in the .ltx file?
Unfortunately it is not possible for me for legal reasons to give the project to an external partner.