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Adventurer
Adventurer
4,720 Views
Registered: ‎03-06-2011

In post P&R simulation, design can't run at the frequency reported in P&R?

Hello,

 

I designed a circuit and P&R report says that this circuit can run at 2.86 ns period. But when I use the 3 ns clock in simulation, design gives many SETUP and HOLD violation errors and circuit could not work properly.

 

FPGA: Virtex-5

Tool: 14.7

 

What is the problem? Is it normal?

 

These are some problems,

at 206050 ps, Instance /testbench/Inst_RegisterFile/Inst_MultiPump_SR_RF_DI_W1_1_29/ : Warning: /X_SFF SETUP  Low VIOLATION ON CE WITH RESPECT TO CLK;
  Expected := 0.103 ns; Observed := 0.1 ns; At : 206.036 ns
at 206050 ps, Instance /testbench/Inst_RegisterFile/Inst_MultiPump_SR_RF_DI_W1_1_28/ : Warning: /X_SFF SETUP  Low VIOLATION ON CE WITH RESPECT TO CLK;
  Expected := 0.103 ns; Observed := 0.1 ns; At : 206.036 ns
at 206060 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R1_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WRADDR(2) WITH RESPECT TO WRCLK;
  Expected := 0.222 ns; Observed := 0.053 ns; At : 206.06 ns
at 206060 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R1_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(2) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(2) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.
at 206078 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R2_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON DI(20) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.151 ns; At : 206.078 ns
at 206078 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R2_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WRADDR(0) WITH RESPECT TO WRCLK;
  Expected := 0.222 ns; Observed := 0.165 ns; At : 206.078 ns
at 206078 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R2_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(0) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(0) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.
at 206090 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WE(0) WITH RESPECT TO WRCLK;
  Expected := 0.432 ns; Observed := 0.107 ns; At : 206.09 ns
at 206090 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WE(1) WITH RESPECT TO WRCLK;
  Expected := 0.432 ns; Observed := 0.107 ns; At : 206.09 ns
at 206090 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WE(2) WITH RESPECT TO WRCLK;
  Expected := 0.432 ns; Observed := 0.047 ns; At : 206.09 ns
at 206090 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WE(3) WITH RESPECT TO WRCLK;
  Expected := 0.432 ns; Observed := 0.047 ns; At : 206.09 ns
at 206095 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R0_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WRADDR(1) WITH RESPECT TO WRCLK;
  Expected := 0.222 ns; Observed := 0.196 ns; At : 206.095 ns
at 206095 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R0_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(1) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(1) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.
at 206121 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R0_Mram_regfile/ : Warning: /X_RAMB18SDP HOLD High VIOLATION ON WRADDR(2) WITH RESPECT TO WRCLK;
  Expected := 0.24 ns; Observed := 0.026 ns; At : 206.121 ns

 

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4 Replies
Teacher rcingham
Teacher
4,693 Views
Registered: ‎09-09-2010

Re: In post P&R simulation, design can't run at the frequency reported in P&R?

Perhaps you need to phase shift the testbench's stimulus w.r.t. the clock to the FPGA.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Adventurer
Adventurer
4,690 Views
Registered: ‎03-06-2011

Re: In post P&R simulation, design can't run at the frequency reported in P&R?

Thanks,

 

I did not enter OFFSET IN and OUT constraints. Only PERIOD constraint. In fact this circuit will not interact with external pads. However when I completed P&R using no IO buffer and not trim unconnected signals options, post PR simulation gives error?

 

Are there any way to simulate in-chip circuits wihout IO pads.

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Highlighted
Teacher rcingham
Teacher
4,684 Views
Registered: ‎09-09-2010

Re: In post P&R simulation, design can't run at the frequency reported in P&R?

But you may still need to phase shift the testbench's stimulus w.r.t. the clock. Try it, and report back.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Adventurer
Adventurer
4,673 Views
Registered: ‎03-06-2011

Re: In post P&R simulation, design can't run at the frequency reported in P&R?

Yes, you are right. Number of the errors decreased however there are still some errors. 

 

This is the phase shifted clock,

 

These are remaining errors. 

 

at 99082 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R1_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP High VIOLATION ON DI(0) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.205 ns; At : 99.082 ns
at 99082 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R1_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP High VIOLATION ON DI(6) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.215 ns; At : 99.082 ns
at 99105 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R2_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP High VIOLATION ON DI(0) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.122 ns; At : 99.105 ns
at 99110 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R2_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP High VIOLATION ON WRADDR(0) WITH RESPECT TO WRCLK;
  Expected := 0.222 ns; Observed := 0.095 ns; At : 99.11 ns
at 99110 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R2_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(0) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(0) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.
at 99269 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning: /X_RAMB18SDP HOLD  Low VIOLATION ON WRADDR(0) WITH RESPECT TO WRCLK;
  Expected := 0.24 ns; Observed := 0.085 ns; At : 99.269 ns
at 99269 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(0) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(0) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.
at 103082 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R1_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON DI(0) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.205 ns; At : 103.082 ns
at 103082 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R1_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON DI(6) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.215 ns; At : 103.082 ns
at 103105 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B1R2_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON DI(0) WITH RESPECT TO WRCLK;
  Expected := 0.27 ns; Observed := 0.122 ns; At : 103.105 ns
at 103110 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R2_Mram_regfile/ : Warning: /X_RAMB18SDP SETUP  Low VIOLATION ON WRADDR(0) WITH RESPECT TO WRCLK;
  Expected := 0.222 ns; Observed := 0.095 ns; At : 103.11 ns
at 103110 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R2_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(0) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(0) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.
at 103269 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning: /X_RAMB18SDP HOLD High VIOLATION ON WRADDR(0) WITH RESPECT TO WRCLK;
  Expected := 0.24 ns; Observed := 0.085 ns; At : 103.269 ns
at 103269 ps(2), Instance /testbench/Inst_RegisterFile/Inst_MultiPort_Inst_BRAM_B0R0_Mram_regfile/ : Warning:  Setup/Hold Violation on WRADDR(0) with respect to WRCLK when memory has been enabled. The memory contents at WRADDR(0) of the RAM can be corrupted. This corruption is not modeled in this simulation model. Please take the necessary steps to recover from this data corruption in hardware.

 

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