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Participant
Participant
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Registered: ‎08-23-2017

Incorrect argument specified with AXI VIP

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Dear all, 

 

I am using the AXI VIP to test my AXI 4 Full Slave device. I have created a SystemVerilog testbench containing a Master agent that is responsible of generating AXI 4 Full Write transactions. I am using the master_agent.AXI4_WRITE_BURST(...) to do the job, where master_agent is my *_mst_t object.

 

However, I get the following error:

 

XilinxAXIVIP: Found at Path: axi_vip_tb.DUT.AXI_VIP_0.inst
INFO: [Master VIP_rd_driver] (.axi_vip_v1_0_2_pkg.axi_mst_rd_driver(C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0)::run_phase.Block10563_775.) 45001 : run()
INFO: [Master VIP_wr_driver] (.axi_vip_v1_0_2_pkg.axi_mst_wr_driver(C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0)::run_phase.Block9555_735.) 45001 : run()
INFO: [Master VIP_monitor] (.axi_vip_v1_0_2_pkg.axi_monitor(C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0)::run_phase.Block8397_719.) 45001 : run()
ERROR: Incorrect argument specified
INFO: [Master VIP_wr_driver] (axi_vip_v1_0_2_pkg.axi_mst_wr_driver(C_AXI_WID_WIDTH=4,C_AXI_RID_WIDTH=4,C_AXI_SUPPORTS_NARROW=0)::get_and_drive.GET_AND_DRIVE) 145000 : Sending transaction:

NameTypeSizeValue

write transactionAXI_TRANSACTION-@17
CMD_IDstring100x00000000
AXI_VERSIONstring4 
CMDstring1
ADDRstring180x00000000c0000000
WIDstring100x00000000
LENstring40x00
SIZEstring1
BURSTstring1
LOCKstring1
CACHEstring30x0
PROTstring30x0
REGIONstring30x0
QOSstring30x0
DRIVER_RETURN_ITEMstring4
CREATION_TIMEstring6145000
SUBMIT_TIMEstring10
BRESPstring17XIL_AXI_RESP_OKAY
PAYLOADarray4-
BEAT[ 0]string400x00000000 (strb : 0b1111) :beat_delay:)

 

I can't understand what's going on, and why shall I get the "incorrect arguments specified" error from the API.

 

Can you please help?
Thanks a lot

 

Simone

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Moderator
Moderator
5,919 Views
Registered: ‎11-09-2015

Hello @scmicron,

 

I have investigate the simulation result and it seems that there is a small issue in the simulation sources for the VIP. But it only affects the display not the behavior (does not display beat delay value).

 

You can ignore this message.

 

This should be resolved in 2017.3.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
3,561 Views
Registered: ‎11-09-2015

Hi @scmicron,

 

Could you share a test case? This is are to tell with only the output from the console.

 

You also may want to have a look at this wiki page I have created:

http://www.wiki.xilinx.com/Using+the+AXI4+VIP+as+a+master+to+read+and+write+to+an+AXI4-Lite+slave+interface

 

This is a really simple example but which shows READ and WRITE burst with the VIP.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant
Participant
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Registered: ‎08-23-2017

Hello Florent, 

indeed the page you mentioned was my starting point ;)

 

Here is my test case: I am trying to write 4 Bytes over a 32-bit wide bus within a single transaction (burst of 1 beat of exactly 4 Bytes). I am enclosing it in a loop to access memory sequentially:

 

axi4_lock = XIL_AXI_ALOCK_NOLOCK;
axi4_cache = 0;
axi4_prot = 0;
axi4_region = 0;
axi4_qos = 0;
axi4_awuser = 0;
axi4_aruser = 0;
axi4_wuser = 0;
axi4_ruser = 0;

axi4_id = 0;
axi4_size = XIL_AXI_SIZE_4BYTE;
axi4_burst = XIL_AXI_BURST_TYPE_INCR;
num_of_bytes = 4; // Bytes to send
axi4_len = num_of_bytes / (2 ** axi4_size) - 1; // Length of the burst to maximize bus usage

 

for(idx = 1; idx <= 4; idx = idx + 1)
begin
   mem_row = idx;
   offset = 4 * mem_row;
   axi4_addr = `AXI_SLAVE_BASE_ADDRESS + offset;
   axi4_data[31:0] = $random;
   master_agent.AXI4_WRITE_BURST(axi4_id, axi4_addr, axi4_len, axi4_size, axi4_burst, axi4_lock, axi4_cache, axi4_prot,    axi4_region, axi4_qos, axi4_awuser, axi4_data[31:0], axi4_wuser, axi4_bresp);


   repeat(50) @(posedge aclk);
end

 

Thanks

Cheers

S

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Moderator
Moderator
3,551 Views
Registered: ‎11-09-2015

Hi @scmicron,

 

indeed the page you mentioned was my starting point ;)

-> Good to know that what I am writing is helping ;)

 

Here is my test case

-> Sorry to ask for more, but could you attach you full vivado project (zipped), ready for simulation.

 

I think I had the same issue as you do if the type of one variable is not corresponding to what the function is expecting.

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant
Participant
3,546 Views
Registered: ‎08-23-2017

Hello Florent,

 

thanks for the feedback, but I cannot send you the entire project: we are using internal GIT repository with our own structure (from the exported simulation in Vivado). However, I can send you the testbench file that includes the types of data as well. The AXI VIP component and our Slave one are hidden in the design_1 module (DUT instance in the testbench).

 

See attachment, hope this helps.

 

Cheers

S

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Highlighted
Moderator
Moderator
5,920 Views
Registered: ‎11-09-2015

Hello @scmicron,

 

I have investigate the simulation result and it seems that there is a small issue in the simulation sources for the VIP. But it only affects the display not the behavior (does not display beat delay value).

 

You can ignore this message.

 

This should be resolved in 2017.3.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Participant
Participant
3,492 Views
Registered: ‎08-23-2017

Hello Florent,

thanks for the message.

 

Just to let you know: indeed the transaction continues (I checked the waveforms). The only inconvenience is in simulation pausing at the ERROR, but it will go on after issuing a run command.

 

 

Thanks for your help

Cheers

 

Simone

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Moderator
Moderator
3,478 Views
Registered: ‎11-09-2015

Hi @scmicron,

 

In my case the simulation does not stop on this error.

 

Could you mark this thread as solved if the answer is enough for you?

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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