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154 Views
Registered: ‎08-01-2019

Independent clock FIFO stays empty

Hi

I am instantiated Block ram fifo without reset in asymmetric mode (write width is 128 and read width 16), fifo write and read clock are independent.(wrtie clcok = 10Mhz and Read clock = 80Mhz).

Block ram fifo taking 4 clock cycle latency  to write the data into fifo, so starting 4 input data are missing to write into fifo.

can any one share the solution for the above problem?   

Regards

Bharath

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2 Replies
Scholar drjohnsmith
Scholar
136 Views
Registered: ‎07-09-2009

Re: Independent clock FIFO stays empty

show us the simulation please,
also check that both clocks are constant,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
Explorer
111 Views
Registered: ‎12-05-2016

Re: Independent clock FIFO stays empty

Hi bharathkcp@gmail.com 

use write data count and read data counts( optional ports, can be enabled from GUI)  in your logic, so that we can ensure that data is available in the FIFO for reading. 

Regards,

Reshma

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