11-14-2017 07:53 AM
Hi, dear sir,
If we design a DMA for the data movement b/w DRAM and internal Block SRAM, is it possible to preload data to the dram in simulation and so we can focus on the verification of functionality of DMA transfer ? If yes, are there any example to initialize DRAM in Vivado simulation env ?
11-14-2017 03:53 PM
It is possible to preload data to the DRAM in simulation, if you use MICRON's dram simulation model.
Please refer MICRON's dram simulation model.
But you might have to modify this simulation model for xsim (Vivado).