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1,913 Views
Registered: ‎03-03-2017

Initializing block RAM for simulation

I am using Vivado 2018.1 and am simulating RTL that contains an instatiation of a block RAM which I have setup to pre-load a COE file.  This pre-setting of the block ram does not seem to take affect in simulation.   Can somebody help me with getting the pre-setting in simulation?

Thanks.  

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7 Replies
1,852 Views
Registered: ‎03-03-2017

Re: Initializing block RAM for simulation

Is there any way to do a $readmemh and have it be applied to the block_memory_inst.inst.memory?

Tim

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Moderator
Moderator
1,848 Views
Registered: ‎04-24-2013

Re: Initializing block RAM for simulation

Hi @tim_severance,

 

You can use the $readmemb or $readmemh Verilog commands to load the data into a BRAM for Simulation.

 

There are examples of the syntax in the Language Templates in Vivado

 

LT.JPG

 

Best Regards
Aidan

 

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1,846 Views
Registered: ‎03-03-2017

Re: Initializing block RAM for simulation

@amaccre,

   Thanks for the information.   I was actually already aware of doing that for a distributed ram setup, but the memory I am using is much too large for distributed RAM so I have to instantiate a block ram instatiation.   Is there way to have the readmem be applied to the block ram instance?

   i did setup the block ram to use a COE for initialization when implemented, but for now I need to simulate before i will be ready to implement.

 

Thanks.

Tim

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1,840 Views
Registered: ‎03-03-2017

Re: Initializing block RAM for simulation

Here is my setup:

 

RTL block containing a block ram instance:

blk_ram_instantiation.png

 

Block ram setup:

blk_ram_setup1.png

bblk_ram_setup2.png

bblk_ram_setup3.png

bblk_ram_setup4.png

 

Memory viewable when I run the simulation, which is not initialized to the COE file values:

blk_ram_sim.png

 

Tim

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1,835 Views
Registered: ‎03-03-2017

Re: Initializing block RAM for simulation

I figure if you do not have a solution to this I will have to do a dummy memory which I do a readmemh with and clock it’s data into the block ram instantiation. 

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Visitor keqian
Visitor
1,500 Views
Registered: ‎08-21-2018

Re: Initializing block RAM for simulation

Hi Tim,

 

I meet same as you met before, initial block RAM for simulation. do you resolve it?

if yes, could you share how to resolve it? thanks.

 

Thanks,

Qian

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Xilinx Employee
Xilinx Employee
1,493 Views
Registered: ‎07-16-2008

Re: Initializing block RAM for simulation

If you specify a .coe to initialize BRAM, the tool should automatically generate .mif in simulation directory. The .mif file is used in simulation so that the initial values are populated. Did you launch Vivado simulation from GUI?

 

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