05-18-2018 05:26 PM
I am using Vivado 2018.1 and am simulating RTL that contains an instatiation of a block RAM which I have setup to pre-load a COE file. This pre-setting of the block ram does not seem to take affect in simulation. Can somebody help me with getting the pre-setting in simulation?
05-21-2018 07:34 AM
You can use the $readmemb or $readmemh Verilog commands to load the data into a BRAM for Simulation.
There are examples of the syntax in the Language Templates in Vivado
05-21-2018 07:37 AM
Thanks for the information. I was actually already aware of doing that for a distributed ram setup, but the memory I am using is much too large for distributed RAM so I have to instantiate a block ram instatiation. Is there way to have the readmem be applied to the block ram instance?
i did setup the block ram to use a COE for initialization when implemented, but for now I need to simulate before i will be ready to implement.
05-21-2018 07:46 AM
Here is my setup:
RTL block containing a block ram instance:
Block ram setup:
Memory viewable when I run the simulation, which is not initialized to the COE file values:
05-21-2018 08:39 AM
I figure if you do not have a solution to this I will have to do a dummy memory which I do a readmemh with and clock it’s data into the block ram instantiation.
09-11-2018 02:07 AM
I meet same as you met before, initial block RAM for simulation. do you resolve it?
if yes, could you share how to resolve it? thanks.
09-11-2018 02:42 AM
If you specify a .coe to initialize BRAM, the tool should automatically generate .mif in simulation directory. The .mif file is used in simulation so that the initial values are populated. Did you launch Vivado simulation from GUI?